SPICE Modeling voltage during battery discharge

batteriesspicevoltage

I am trying to create a spice model of a battery discharging into an LED.

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I would like to model the charge remaining (Ah) throughout the discharge and as I understand it this can be acheived by reading the voltage across the terminals of the battery.

I would like to model the discharging of the battery and view the voltage across the terminals over time.

I am just starting to use spice models and have been playing around with pspice, ltspice and now circuit-lab.

Best Answer

A good model of a battery would keep it as a voltage source, but add a resistance in series with it (separate from your external 220R resistor).

Then you need to find a way of increasing that resistance as the product of current draw and time increases.

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Electronic – How to modify spice transistor model

You can, rather easily, hand translate it. The biggest headache is making sure you've got the correct variables defined.

Going off of this: http://www.youspice.com/ys/bjtfromdatasheet.3sp

And comparing it to one of the LTSpice models that is in this: LTSpice

It looks like LTSpice follows the same conventions as PSpice models, so my assumption is that the model information housed in the LTSpice link is correct for more than just LTSpice (haven't tested against NGSpice, but it's just a Berkley Spice program so it shouldn't be any different), you just need to add a new BJT with those model parameters that are outlined in the links.

EDIT: Looking even further, even AIM-Spice has the same model setup for a BJT. I'm extremely confident that as long as you translate parameters correctly you can take any spice model and move it from one spice program to another, assuming it's at least using the basic Berkley Spice setup

Electronic – From curves to SPICE model

You could start with a SPICE model of the transistor in a CD4007 and fiddle with the parameters to get it to match your curves.

**************************************************
* Level 1 SPICE Models for the 4007 CMOS chip
**************************************************
* These Level 1 models were extracted from measured results. The
* model attempts to account for the package parasitics. The simulated and
* typical measured device capacitances are as follows:
*
*    NMOS: Cgs = 18pF   Cds = 14pF
*    PMOS: Cgs = 17pF   Cds = 26pF
*
* Gate-to-drain capacitances were not extracted but were adjusted to
* to help fit measured results.

*$
.MODEL CMOSP    PMOS    ( LEVEL   = 1           L=5u    W=100u                
+VTO    = -1.40         KP      = 3.2e-5        GAMMA   = 3.30  
+PHI    = 0.65          LAMBDA  = 9e-2          CBD     = 65e-12
+CBS    = 2e-14         IS      = 1e-15         PB      = 0.87
+CGSO   = 0             CGDO    = 0             CGBO    = 1e-5
+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9
+MJSW   = 0.33          JS      = 1e-8          TOX     = 6.89e-10)
*$
.MODEL CMOSN    NMOS    ( LEVEL   = 1           L=5u    W=20u             
+VTO    = 1.77          Kp      = 2.169e-4      GAMMA   = 4.10  
+PHI    = 0.65          LAMBDA  = 1.5e-2        CBD     = 20e-12
+CBS    = 0             IS      = 1e-15         PB      = 0.87
+CBS    = 2e-14         CGDO    = 88e-8         CGBO    = 0
+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9
+MJSW   = 0.33          JS      = 1e-8          TOX     = 1.265e-10)

**************************************************
* Macro for 4007 IC:
**************************************************
*
* Pinout:
*
*             S4/psub G1,4 D5   S5   G5,2 S2   D2      * 1,2,3 - PMOS
*               _||___||___||___||___||___||___||_     * 4,5,6 - NMOS
*               | 7   6    5    4    3    2    1 |     * All PMOS susbstrates 
*               |                                |       connected to pin 14
*               |                              * |     * All NMOS susbstrates
*               |                                |       connected to pin 7
*               | 8   9    10   11   12   13   14|
*               _  ___  ___  ___  ___  ___  ___  _
*                ||   ||   ||   ||   ||   ||   ||
*                D4   S6   G3,6 S3   D3,6 D1   S1/nsub
*
* General Form of subcircuit call:
*  X1 n1 n2 ... n14 CMOS4007
*
*$
.SUBCKT CMOS4007 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* MOSFET DR GT SRC SUBS MODEL L    W
M1       13 6  14  14   CMOSP L=5u W=100u
M2       1  3  2   14   CMOSP L=5u W=100u
M3       12 10 11  14   CMOSP L=5u W=100u
M4       8  6  7   7    CMOSN L=5u W=20u
M5       5  3  4   7    CMOSN L=5u W=20u
M6       12 10 9   7    CMOSN L=5u W=20u
.ENDS CMOS4007
*

*$

Best Answer

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