Split supply common-emitter design

Your electronics class has probably taught you the hybrid-pi model and given you some complex (yet accurate) formulas for gain, input resistance, and output resistance of the various amplifier topologies. It might help your understanding to have some simpler, approximate formulas. These come from the always-helpful Art of Electronics by Horowitz and Hill.

^{simulate this circuit – Schematic created using CircuitLab}

$$Current\ gain = \frac{I_C}{I_B} = h_{FE} = \beta$$

$$Input\ resistance\ of\ the\ base: \beta R_E$$

$$Output\ resistance\ of\ the\ emitter: \frac{R_S}{\beta} || R_E$$

$$Output\ resistance\ of\ the\ collector: R_C$$

$$Voltage\ gain = \frac{V_C}{V_{in}} = -\frac{R_C}{R_E}$$

These formulas are based on the following assumptions, some of which may be interchangeable:

• \$\beta\$ is large

• \$R_E >> r_e\$

• The voltage drop across the base-emitter junction is constant

• The collector current is not too large

As \$R_E\$ gets smaller, the inherent emitter resistance starts to have a bigger effect on your gain. As the collector current gets larger, the transistor starts acting less like an ideal current source. This is where the \$r_\pi\$ and \$r_o\$ terms from the hybrid-pi model come in. In particular, the common case of a bypassed emitter resistor (which gives you the high gain you need) requires the hybrid-pi model.

As you can see, using series resistors to directly control the input resistance is not necessary. The emitter resistor's value gets multiplied at the base. Just make sure your biasing resistors are large, and you should be fine. As you suspected, a common collector amplifier will give you the output resistance you need.

The design is a bit off in some areas, first the FET biasing scheme is fine but its a bit of downside as you will limit the input impedance, you should aim for a self biasing scheme, FET will not give you a gain typically more than 4 times so its up to the later BJT to exact the gain.

Let Re in both stages be split to 2 resistors, with the lower in parallel with bypass cap, your lower frequency limit is calculated by the bypass cap \$ value = \frac{1}{ 2*pi*R*C} \$ where R is the resistance in parallel, for high frequency limit you should connect a cap between collector and ground or Vcc and calculate the value the same but with the resistor being the collector resistor.

For gain assume Ic = 1mA, Ve = 1V so Re = 1Kohm, since gain is Av= -Rc/Re1 just set the Rc to a value like 2K and a gain of say 10, then Re1 = 200 ohm, since Re total = 1 K then the bypassed resistor is 1k -200 = 800, assume that first stage a gain of 2, second stage a gain of 10 and third stage a gain of 5, then total gain is 2 * 10 * 5 = 100

For the FET use a self bias scheme with 1 - 10 Meg resistor and set the current for example to 1mA, since you want it to work in active mode, then RgIg - RsId - Vgs = 0; since Ig = 0; then RsId = -Vgs, Vgs = -4V, Id = 1mA, then Rs = 4Kohm, you can as well split and do the bypass trick to get a higher gain = -Rd/Rs otherwise it would be Av= -gmRd

I forgot to add the higher frequency limit capacitor, add it in the last stage from collector to Vcc before the decoupling cap, for feedback take a line from R8 top through a resistor and capacitor up to R14 top (input of Q1), I not that experienced with Feedback but I think it sould do a shunt-shunt feedback.