The meaning of fault_reg = ram [address] in verilog

verilog

input [3:0] address; 
reg [3:0] ram [7:0];
reg [3:0] data, fault_reg;
fault_reg = ram[address];
data = fault_reg;

If the value of ram is 1010 and the value of address is 100, what is the value of data[0], data[1], data[2] and data[3]?

Does it mean data[0] mean bit No.0 = 0 of ram, data[1] mean bit No. 1 of ram = 1, data[2] mean bit No.2 = 0 and…..?

Best Answer

Here, address is four bits wide and ram is declared as reg [3:0] ram [7:0];. This declares a memory as nibble (4-bit) wide and such 8 nibbles.

As shown in below figure.

In order to fully address all the 8 memory addresses, only 3 address bits are sufficient. So, there is an unused bit in address variable. This will not give any simulation issues, but synthesis tool shall give warning about the unused bit of address.

Also, declaring reg [3:0] data gives 0 as Least Significant bit (LSB) and 3 as Most Significant bit (MSB). So, for your question:

What is the meaning of fault_reg = ram [address] in verilog?

This assigns/copies value from memory ram at address of address to fault_reg.

If the value of ram is 1010 and the value of address is 100, what is the value of data[0], data[1], data[2] and data[3]?

In this example, ram[4] = 4'b1010 so, ram[4][0]=0,ram[4][1]=1,... and so on. Hence, data[0]=0, data[1]=1, data[2]=0, data[3]=1.

Refer to Verilog Array Input question for unused address bit and Verilog Memory, Simple RAM Model links for further information.

Related Solutions

Electronic – Mapping address ranges in Verilog

Verilog can handle the chip select approach - the high impedance state is called Z.

However, whether synthesis can handle it depends on whether whatever you're trying to synthesize to has the necessary tristate drivers available, and whether the synthesis program knows how to use them.

Disconnecting inputs from the bus isn't necessary; just the outputs.

It worked this way back when I specialized in ASIC and FPGA logic simulation using Verilog.

Your mapping the address bus method isn't clear enough that I can say much on that.

Electronic – using ram verilog instantiation

You'll need to use the clock to break up the write and read operations. Here is an example of a test bench that writes data to two addresses then reads them back.

wire [DATA_WIDTH-1:0] data = we ? wdata : {DATA_WIDTH{1'bz}}; // tri-state write output driver
ram i_ram0(clk,we,addr,data);

initial begin
  clk   = 1'b1;
  data1 = 'h0F;
  data2 = 'hF0;
  addr1 = 0;
  addr2 = 2;
  we    = 1'b1;
  addr  = addr1;
  wdata = data1;
  @(posedge clk) #1;
  addr  = addr2;
  wdata = data2;
  @(posedge clk) #1;
  we    = 1'b0;
  addr  = addr1;
  @(posedge clk) #1;
  if(data !== data1) $display("ERROR data:%h != data1:%h @ addr:%h", data,data1,addr);
  addr  = addr2;
  @(posedge clk) #1;
  if(data !== data2) $display("ERROR data:%h != data2:%h @ addr:%h", data,data2,addr);
  @(posedge clk) #1;
  $finish;
end

FLY if data is an inout, then you need a tri-state driver in your ram module:

assign data = we ? {DATA_WIDTH{1'bz}} : rdata; // tri-state read output driver

Full working example here: http://www.edaplayground.com/s/6/221

Best Answer

Related Solutions

Electronic – Mapping address ranges in Verilog

Electronic – using ram verilog instantiation

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