The real ADC Sample rate for Xmega256A3BU or similar xmega controllers

Many ADC input circuits will connect a capacitor with an unpredictable charge state to the input they're about to sample. If the input is a very low impedance source and won't "budge", this won't pose a problem; that capacitance will quickly match the voltage on the input. If the input is a moderate-impedance source but has very low capacitance, connecting that capacitance may disturb the voltage on the input, but the voltage on the input will relatively quickly return to the correct value. If the input is a high- or moderate-impedance source and has a huge amount of capacitance of its own (e.g. for a 12-bit ADC, it exceeds the sampling capacitance of the ADC by a factor of a few thousand), and if readings are not taken too frequently, the big capacitor may be considered a low-impedance source that won't "budge". If, however, the input has a capacitance that is e.g. 50 times the input sampling cap, then connecting the sampling cap may disturb the input voltage by 1/50 of full scale (a big disturbance) but the increased capacitance may increase 50-fold the RC time constant for its returning to normal.

If the ADC waits long enough between connecting the input capacitance and taking a reading, any disturbance caused by switching the input capacitance will likely settle out. On the other hand, there are some situations where such settling time isn't needed but rapid readings are. Making the acquisition time programmable allows both types of situations to be accommodated.

If you look at Table 2, you'll see that the MD0 and MD1 pins control how the master utilizes the clock input (either 256, 384, or 512 * fs). Once you select one of these options, you can use your crystal frequency to tell you the sampling frequency.

Once you know the sampling frequency, you can use the resolution to give you the BCK rate. This particular part has 24-bit resolution. Each "frame" of audio consists of two channels, left and right. Each channel has a 24-bit value. Therefore, each sample is 24-bits of data. If, for example, you are using 64KHz sampling rate (by selecting 256fs using MD0 and MD1 pins), then you can get the BCK rate:

24 bits/sample * 64,000 samples/sec = 1,536,000 bits/sec

Therefore, your BCK frequency is 1.536 MHz. Your L/R clock will be 24 times slower than this, since it oscillates when the channel switches, which is every 24 bits.