Auto Boot Circuit – Understanding Auto Boot Circuit

arduinoesp32

I'm trying to figuring out how this circuit works instead of just simply ripping it off from schematics found on the internet.

I've seen this circuit on many designs (ESP32 Dev board and Heltec CubeCell dev board, etc.)

Here is the schematic from Haltec:

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I found it hard to read so I've re-arranged the components like this:

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This is how I've understood it so far (also using the table given from the first schematic.)

When the DTR line is pulled low, this make the NMOSFET U5 non-conducting. I'm not sure about the purpose of C6 which is kept at 5V through R11 (maybe to prevent the RESET line from being LOW due to noise or sudden current draw).

Now RTS is pulled low: again U2 is non-conducting since the gate of U2 is at 0V and the source is also pulled low by DTR.

Now RTS is pulled high: the source of U2 being at 0V due to DTR still being pulled LOW and the gate of U2 being at 5V thanks to RTS, current can flow between U2 drain and source which make the BOOTLOADER/IO16 line LOW (on the CubeCell module: IO16 is equivalent to IO0 on ESP32 when being LOW on boot bring the chip into boot loader mode.)

Finally DTR is pulled high: this is where I have trouble understanding what's happening.

I understand that the RESET line should be pulled LOW somehow in order to reset the board, but Vgs on U5 isn't supposed to be 0V when both DTR and RTS are HIGH.

I also came across this page where the author tried to explain the programing circuit from the Arduino board, where somehow (and I didn't understand why) the capacitor can reach up to 10V while being pulled high with only 5V.

Best Answer

Here is how I interpret the circuit functions:

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The push buttons can be ignored, but I included (state c) to show the RESET button has priority over everything else. Note that state transitions e,f,g can be simulated with the press buttons by holding RESET and USER1, then releasing RESET, hence causing the boot loader to run.

I believe C10 is there to address the race condition when RTS goes 0->1 in state g.