Verilog Netlist and verilog file not justifying each other

synthesisverilog

i generated a verilog netlist file with the help of a test case for 2-1 encoder .To test the netlist i draw the schematic diagram and try to find the output.I can't upload the pic of schematic which i draw by hand but below is the verilog file

module test (input [1:0] in, input enable, output reg  out);

always @(in or enable)
    if(!enable)
        out = 4'b0000;
    else begin
       case (in)
           2'b00 : out = 0 ;
           2'b01 : out = 1;
           2'b10 : out = 0;
           2'b11 : out = 1;
        endcase
    end
endmodule

which says that output must be 0,1,0,1

i generated a netlist which is given below

module test(enable, in, out);
input [1:0] in;
input enable;
output out;

wire  synth_net_4;
wire  synth_net_9;
wire  synth_net_12;
wire  synth_net_17;

wire  synth_net_19;
wire  synth_net;
GND synth_GND_0(.out(synth_net_4));
GND 
    synth_GND_1(.out(synth_net_12));
MUX4 synth_MUX(.in({synth_net_17, 
    synth_net_12, synth_net_9, synth_net_4}), .select({in[1], in[0]}), .out(
    synth_net_19));
VCC synth_VCC_2(.out(synth_net_9));
VCC synth_VCC_5(.out(
    synth_net_17));
BUF synth_BUF(.in(enable), .out(synth_net));
AND2 synth_AND(
    .in({synth_net_19, synth_net}), .out(out));
endmodule

but schematic with respect to this netlist give output as 1,0,1,0.So am i doing something wrong in getting exact schematic?I just want to validate that netlist corresponds exactly to verilog file.

Best Answer

The output only depends on enable and in[0], resulting in the following coding optimization:

module test (input in, input enable, output out);
assign out = enable & in;
endmodule

where in is the old in[0], and the output has been changed to a wire type. Normally, a synthesis tool would do that optimization for you, but here it clearly does not. Optimizing your code yourself will make a circuit which is just one gate instead of 3 gates as in your current result.

I drew the schematic of your netlist and there is not enough information to know if it matches the RTL. I would need to know how the MUX4 module maps the inputs based on the select signal. You can see the "??" which represents some combination of in1 and in[0]. But it is not known which combination selects which input, since you didn't attach the MUX4 model.

enter image description here

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