VHDL Plus operator `+` and Downto syntax

fpgavhdl

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have a + b as 33 bit result;

How can we get 32 bits out of this?

Does VHDL have something like (a+b)(31 downto 0) or we should store c:= a+b and then get c(31 downto 0)?

Best Answer

If a, b, c are of type std_logic_vector(31 downto 0),

then, c := a + b;
will give the 32 bit answer in c (without carry) as you required.

If you want 33 bit answer in c (where c is std_logic_vector(32 downto 0))

Then c := ('0' & a) + ('0' & b) will give the 33 bit answer.

But you will need ieee.std_logic_unsigned package for adding std_logic_vector using + operator.

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VHDL – Convert from binary/integer to BCD and display it on the 7-segment display

In VHDL (and HDLs in general) a for loop does not denote sequential execution like it does in a software programming language — it denotes the construction of multiple parallel instances of the hardware described in the body of the loop.

In your case, you have many assignments to the same variable BCD/bcd, and these are conflicting with each other. If you really intend to construct a system based on two shift registers (one binary, one bcd) that takes 14 clock periods to do the conversion, then you need to describe the hardware that way, and set up a state machine to control it.

On the other hand, if you really want to do it entirely combinatorially, then you need to create different intermediate variables (e.g., arrays that are indexed by the loop control variable) to hold the results at each stage.

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Best Answer

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