I am trying to interface a micro-controller (LPC11C14) to a LCD. The LCD has Vih = 3.5V so I cannot directly connect the uC pin to the LCD. For this, I found a GTL2000 chip which looks like it might do the job. But here is the issue that i am not sure about.
I want bi-directional voltage translation because I want R/W facility with the LCD (for reading Status Read). I know that I can set the outputs of this CMOS microcontroller to open-drain, but I am not sure about the LCD (I don't think they are open drains). So I modified the bi-directional circuit shown in the datasheet to include resistors on the open drain side. The clamp resistors are calculated through specified formulas in the datasheet. GTL 2000 Example circuit
My question is this circuit likely to work?
Also, if I don't put the uC pins in open drain mode, I can remove the pull-up resistors on that side. Is that possible as well? The datasheet does not talk about standard GPIO behavior.
Thanks,
The LCD being is NHD-12864WG-BTGH-T#N, which has a Voh of 3.5V.
Best Answer
You'd have to provide additional information about which LCD you're using. In general, though, what you are proposing will not work.
You can connect multiple open drain outputs together because open drain logic is essentially an OR of all the outputs. Each output only sets logic 0 or a don't care condition, so it's safe to connect multiple drivers together, and there is no contention. You cannot do this with a regular output (what the datasheet calls a totem pole output), because such an output asserts both logic 0 and logic 1. This means that there is scope for significant contention between the two sides. In your case, the circuit will simply not work, and likely cause a fair bit of damage.
Parallel buses are very rarely open drain. Just because you can set an output as open drain does not mean that it will remain open drain if you enable a bus controlling peripheral like an SMC (Static Memory Controller) and/or DMA. I haven't used the LPC myself, but I'd be very careful with it. Generally, as long as you use it as a GPIO it'll honour the open drain setting. Once you enable a peripheral, then it depends on the peripheral's requirements. Usually, open drain isn't fast enough a high speed parallel bus, and therefore they aren't designed to handle open drain.
The general way to handle voltage translation for such applications is to use high speed logic, and a combination of the WR/RD and CS pulses to set the direction of a more traditional level translating buffer like the SN74LVC1T45 and it's 2, 8, 16 bit variants. Given information about which lines need reversing and when, you can work out a scheme which does what you require.