It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that tests the DUT.
Anyway, there does seem to be a lot of terminology involved in this as well and at this point I only wish to know what is code coverage and especially functional coverage. These terms are also used with reference to SystemVerilog that I am trying to read about.
Edit:
Just one more question here. What is a "configuration" in systemverilog?
The book says "Generate configuration : Randomize the configuration of the DUT and the surrounding environment." What does that mean?
Best Answer
Code coverage is a metric that tells you if you have executed each line of code in the implementation of your design. There are a number of other metrics for code coverage that tools can easily calculate for you non-intrusively (e.g has each single toggled to their true and false states). The theory is that you could not have tested code that was never executed. But code coverage does not tell you anything about the correctness of the code that executed. Therefore it is a necessary but insufficient verification metric.
Functional coverage is a metric that tells you if you have tested all the required functionality of a design. Supposedly when someone sits down to create a design, they have a specification that lists all the feature that the design needs to provide. There are a number of ways to collect functional coverage data, but typically you need to track a test for each feature or set of features, and that the test succeeded to mark a feature as functionally covered. No knowledge of the implementation of the design is needed.
You may want to look at our Coverage Cookbook for more information.