What operation does this circuit perform

binarylogic-gates

I have an assignment due for school, but this one question has been getting the best of my group-mate and I for about a week now. I am in no way asking you to solve the problem for me, but could you please make it a little bit simpler for us to understand.

Question:
If the input and output bit patterns in the circuit below are interpreted as binary representations of numeric values, what operation does the circuit perform?

My thinking:

1) If we put in a set of ones and zeroes as input then determined what the output would be , then convert the input bit pattern and output pattern to decimal, then we could try to figure out what base 10 mathematical operation was performed. Although when this was tried, there seemed to be no simple correlation between the input and the output.

2) Assuming that the question is not looking for a mathematical operation , and is instead looking for a logical operation, we tried drawing up a truth table, then go stuck("Where do we go from here? ").

Problems:

1) The question stated that the input and output bit patterns are binary representations of numeric values, we cant figure out why that is important , because when trying to do base ten arithmetic, it did not work.

2) Why did they put the '1' as an input?

3) assuming three inputs, how to you go about finding out what single logical operation is performed in the circuit.

Best Answer

Have another go at the numeric hint. The question told you they were binary values.

We normally write binary values left to right, same way as we do for decimal values. So the left hand column is most significant, so weight 4, and the right most column is least significant, weight 1.

You understand XOR gates, right? One way to look at them is 'they do the exclusive OR thang'. Another way to look at them is that they pass through a logic signal unchanged when the other input is 0, and invert it when the other input is 1. The logic operation described is identical, but sometimes it's easier to get what a circuit is doing using one or the other way.

If you look at the logic operation, a pattern emerges.

The '1' output is always inverted.

The '2' output is inverted when the '1' input is low.

The '4' output is inverted when both the '1' and '2' inputs are low.

That sequence is screaming out a pattern to me, like it's meant to do something sensible.

Anyhow, I'm not going to do your homework for you. You started in the right way, writing down all 8 sets of ones and zeroes. However if the answer didn't jump out at you, perhaps you picked a non-standard weighting. Try again with the weighting I suggest and have another look.

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Electronic – Mathematical Logic behind generating T0 codes

According to the paper found by @lustful-rat, T0-C is not a method for encoding binary words individually, but rather a method of encoding sequences of binary words. It is used in situations in which the sequences frequently contain groups of values that are a fixed offset from each other, such as stepping through a memory array by bytes or words.

The transmitter and receiver agree on a step size \$S\$. If the next value to be transmitted is the previous value plus S (i.e., \$b(t) = b(t-1) + S\$), then the actual value on the bus is not changed (\$B(t) = B(t-1)\$). Otherwise, the next value is placed on the bus (\$B(t) = b(t)\$).

However, there is a problem: What if the next value to be transmitted is not the previous value plus S, but it happens to be the same as the current value on the bus (\$b(t) = B(t-1)\$)? In that case, there is only one value that the receiver should NOT be expecting to see, and that is \$b(t-1) + S\$, because if that really were the value to be transmitted, the transmitter would simply keep the bus at \$B(t-1)\$. So if the transmitter actually puts that value on the bus, then the receiver knows that this is a special case, and that \$b(t)\$ should now be set to \$B(t-1)\$.

As long as the sequence of values frequently contains sequential values, this method reduces power consumption by greatly reducing the number of transitions on the individual bus wires. In order to implement it, both the transmitter and the receiver need to keep track of \$b(t-1)\$ and \$B(t-1)\$ internally, so that the logic described above (and in the paper) can be constructed.

Transmitter                        Receiver
-----------                        --------
Inputs: b(t-1), b(t), B(t-1)       Inputs: b(t-1), B(t-1), B(t)
Output: B(t)                       Output: b(t)

if (b(t) == b(t-1)+S)              if (B(t) == B(t-1)) 
  B(t) = B(t-1)                      b(t) = b(t-1) + S
else if (b(t) == B(t-1))           else if (B(t) == b(t-1)+S) 
  B(t) = b(t-1)+S                    b(t) = B(t-1)
else                               else 
  B(t) = b(t)                        b(t) = B(t)

Electrical – Converting signed magnitude binary to signed 2’s complement

some numbers like -0 in particular cannot be represented. is there a difference between +0 and -0? There is one or maybe two (or few)numbers that are a problem and they are around the end points. 10000 being minus zero if you see the sign bit set you negate the other bits, invert and add one so 1111 + 1 = 10000 or 0000, leaving you with the number 10000 in twos complement which is what -32 not -0. what about sign magnitude 11111 minus 15. 10001, that works fine. what about 00000 that works fine what about 01111, that works fine. so you have the one exception, if the sign is 1 and the magnitude is zero then flip the sign, else negate the magnitude and keep the sign.

Best Answer

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Electronic – Mathematical Logic behind generating T0 codes

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