Why can’t regs be assigned to multiple always blocks in synthesizable Verilog

verilog

The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It's clear that in a lot of cases assigning a reg to multiple always blocks is meaningless. However, it's seems that there could be hardware-meaning instances of a reg in different always blocks.

For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.

Why is there a "hard rule" concerning regs in different always blocks?

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For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.

The case you mention will not be synthesizable. The flip-flop that implements the reg can only be clocked from one source.

As an aside, I'd like to clarify that the rule about regs having affinity to always blocks affects synthesizability, not validity. Software simulator will handle assignments from different always blocks without any problems.

Related Solutions

Electronic – Beginner with fpga and timing issues

Have I understood that situation correctly?

Yes - if some part of your output data is available later than other parts, you have to delay the other parts so they line up.

It's not a fudge, or a "bad" thing to do - it's just what has to be done to make the outputs right.

I could probably buffer the sync pulses too and delay them in the same way.

That's what I'd do. (EDIT: And as Yann reminded me, delaying signals can be very cheap in Xilinx FPGAs - 16 ticks can fit in a single look-up table + 1 more in the flipflop that's next to the LUT)

Or I could pre adjust the calculated memory address to compensate in advance.

That's another option, but will probably take more logic.

Electronic – Procedural blocks in verilog

Does that affect the timing of these signals?

Not really.

Yes a&b are evaluated sequentially but in the same simulator timestep, not seqential in terms of electronic design.

initial begin
  a = 1'b0;
  b = 1'b1;
end

a and b are essentially evaluated in parallel. but your simulator can not do that, the only time that this needs careful consideration is if you rely on previous results.

The following are just examples and would imply latches in some case and should not be used in RTL like this.

always @(posedge clk) begin
  a = y;
  b = a; //this is b=y
end

is not the same as:

always @(posedge clk) begin
  b = a;     //This is old y
  a = y;
end

For clocked systems (implying flip-flops) we use non-blocking (<=) the following 2 examples are the same:

always @(posedge clk) begin
  a <= y;
  b <= a; //this is old y
end

always @(posedge clk) begin
  b <= a;     //This is old y
  a <= y;
end

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Related Solutions

Electronic – Beginner with fpga and timing issues

Electronic – Procedural blocks in verilog

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