Why there are two or more PCIe Hard IPs in some FPGAs

Did You try typing "PCI Express" in Google and give it a shot to feel lucky, huh? Wiki clearly says:

At the electrical level, each lane consists of two unidirectional LVDS or PCML pairs at 2.525 Gbit/s.

http://en.wikipedia.org/wiki/PCI_Express

All a DCM can do is add jitter - it's a tapped delay line, so the output clock can jitter as the taps change. And for the same reason it can't remove any jitter that is already there.

If you want to "clean up" the clock signal, you need to use a PLL - check the datasheet to see if the FPGA PLLs can cope with the spread-spectrum PCIe clock. Or use a dedicated clock cleaning PLL device.