Writing batch files for simulation in Modelsim/QuestaSim

modelsimsimulation

I am trying to compile a design that consists of multiple files. There are library files with the primitives, than netlist files for the design, test vectors files used with the testbench and the test bench file itself. There are multiple cases that need to be tested and for this I may have to write a lot of testbenches and a lot of vector files in which only a couple of lines or so change. I think that it should be possible to use "pre-processor" directives in the verilog to simplify this task. Thus I write a batch file that has a list of vlog commands to compile everything. Within it I define some constant (like we do with #define in C language). Later in the verilog vector and testbench file I can use `if to find out if some part of the file should be compiled or excluded.

Now I have done this type of thing in C but not verilog. Can someone provide me with what steps and commands I need to use. Please note that I shall write a batch file with list of vlog commands and call it from within QuestaSim using the do command. This will compile all files that I need for simulation and also is expected to contain the "constant". Within the testbench I want that depending on value of someconstant "passed to it", different sections of the code in the file will be compiled. These different sections are enclosed in ifdefendif This can be done in C using #ifdef, #endif, #ifndef, and #define pre-processor directives. Note that I am using QuestaSim which is similar to ModelSim, more like its big brother. I have never used this "pre-processor" feature of verilog before.

The problem is that, the batch file contains commands for questasim while the files being compiled contain verilog instructions for hardware description.

So the question is, how do I do this or is it even possible to do this?

Best Answer

Forget the Verilog preprocessor for this. Put Questa/ModelSim on your path and use a makefile to drive the vlog/vsim commands, run it all from the command line. This works natively on Linux, or Windows if you use Cygwin.

EDIT

Here's an example of a complete Makefile that shows how I typically specify my target modules. This uses features specific to GNU make.

# Modules for the actual device
DUT_MODULES = dut_top dut_module1 dut_module2

# Modules for the simulation testbench
TB_MODULES = tb_top tb_module1 tb_module2 tb_module3

# Convert module names into full target paths
DUT_TARGETS = $(foreach mod, $(DUT_MODULES), $(WORK)/$(mod)/_primary.dat)
TB_TARGETS = $(foreach mod, $(TESTBENCH), $(WORK)/$(mod)/_primary.dat)

WORK = work

# Default 'make' target
tb: $(DUT_TARGETS) $(TB_TARGETS)

# Rule for device modules
$(WORK)/%/_primary.dat: ../rtl/uwb_top/v/%.v
    vlog $+

# Rule for testbench modules
$(WORK)/%/_primary.dat: ../testbench/v/%.v
    vlog $+

UPDATE (2017)

Modelsim/Questasim no longer store compiled code in the manner described above; instead, a set of files containing a database is used, and the names of compiled modules are hidden inside them.

However, the changes to the Makefile to accommodate this are straightforward. First, remove the /_primary.dat from the target path expressions. Second, add a touch command that creates an empty file with the same name as the target module after each vlog command. The Makefile becomes:

# Modules for the actual device
DUT_MODULES = dut_top dut_module1 dut_module2

# Modules for the simulation testbench
TB_MODULES = tb_top tb_module1 tb_module2 tb_module3

# Convert module names into full target paths
DUT_TARGETS = $(foreach mod, $(DUT_MODULES), $(WORK)/$(mod))
TB_TARGETS = $(foreach mod, $(TESTBENCH), $(WORK)/$(mod))

WORK = work

# Default 'make' target
tb: $(DUT_TARGETS) $(TB_TARGETS)

# Rule for device modules
$(WORK)/%/_primary.dat: ../rtl/uwb_top/v/%.v
    vlog $+
    touch $@

# Rule for testbench modules
$(WORK)/%/_primary.dat: ../testbench/v/%.v
    vlog $+
    touch $@

These extra files do not interfere in any way with the simulator, and the rest of the Makefile works the same as before.

Electronic – How to compare waveforms from multiple simulations in QuestaSim/ModelSim

You need to save two waveforms/datasets as .wlf files. See 'Saving a Simulation to a WLF file' in the QuestaSim manual. Then you can compare those separate datasets by going under Tools > Waveform Compare > Start Comparison. Also, see 'Waveform Compare' in the QuestaSim manual. It is pretty straight forward.

Best Answer

Related Solutions

Electronic – How to find out if library has already been compiled in ModelSim/QuestaSim to speed up simulation scripts

EDIT

UPDATE (2017)

Electronic – How to compare waveforms from multiple simulations in QuestaSim/ModelSim

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