VHDL multiple std_logic_vector to one large std_logic_vector

vhdl

I have four std_logic_vectors (15 downto 0) and want to stack them into a std_logic_vector (63 downt 0) so fare I have found one way of doing it but is it the correct way or is there a more optimal and correct way to do it?

signal slv16_1,slv16_2,slv16_3,slv16_4 : std_logic_vector(15 downto 0);
signal slv64 : std_logic_vector(63 downto 0);

slv64(15 downto 0) <= slv16_1;
slv64(31 downto 16) <= slv16_2;
slv64(47 downto 32) <= slv16_3;
slv64(63 downto 48) <= slv16_4;

Best Answer

An easy way to accomplish this is to use the concatenation operator &. It achieves the same thing you did above, but with less code required.

slv64 <= slv16_4 & slv16_3 & slv16_2 & slv16_1;

Related Solutions

Vhdl Type mismatch error

The error message tells you exactly what the problem is:

error : Error (10381): VHDL Type Mismatch error at ArrayDivider.vhd(53): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression

And indeed, tempz(Ny-2 downto 0) is not a std_ulogic but a vector.

The problem is that named association does not identify slices of a vector but individual elements; you can't use it to assign one slice of one vector to a slice of another vector.

Instead, use the concatenation operator &,

tempx <= tempz(Ny-2 downto 0) & ipx(a-1);

Your post implies that concatenation produces other errors; feel free to add these to the question.

EDIT :

>Error (10028): Can't resolve multiple constant drivers for net 
>"tempx[0]" at ArrayDivider.vhd(44) (on the line of initialing >tempx)

Again this tells you what is wrong. This error is almost certainly there in both versions of the design, but the original error just hides it. Find the two drivers for tempx(0) and eliminate whichever is the wrong one. You haven't posted enough of your code to make it clear what's going on so that is up to you. If you're using Modelsim, the "drivers" command will identify all the drivers on a signal.

If you need to initialise tempx to the input signal and then later drive it with another signal, you must select between the two signals - for example:

tempx <= ipx(Nx-1 downto Nx-Ny) when <some condition>
         else tempz(Ny-2 downto 0) & ipx(a-1);

Most likely, fixing this error will also eliminate the "hierarchy" error; which is basically "something went wrong earlier so compilation cannot be completed".

Adding 2 std_logic_vector in variable type VHDL

First of all you've included the standard library numeric_std and the nonstandard library std_logic_arith together. They conflict with each other so get rid of std_logic_arith.

Both of those packages implement arithmetic using the unsigned and signed types. It is strongly recommend that you use these types if you want to do arithmetic on vectors. It makes it explicitly clear that you want them interpreted in a numeric context. There is no "+" operator defined for the std_logic_vector type implemented in std_logic_1164 which is why you get an error. You can augment that type with arithmetic operators in VHDL-2008 by also including numeric_std_unsigned. Again, it is better to just use the traditional unsigned type:

A : in unsigned(31 downto 0);
B : in unsigned(31 downto 0);

...

process(AluOp)
  variable temp : unsigned(32 downto 0);
begin

  temp := resize(A, temp'length) + B;

The length of the left and right sides of the assignment have to match so first resize the A signal, expanding it to 33 bits before adding the 32-bit signal B.

Best Answer

Related Solutions

Vhdl Type mismatch error

Adding 2 std_logic_vector in variable type VHDL

Related Topic