VHDL std_logic_vector indexing with “downto”

indexingvhdl

I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have:

signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= (                        5=>'1',     -- Instruction defined
                                    4=>'1',     -- Data length control bit, high=8bit bus mode selected
                                    3=>'1',     -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
                                    2=>'0',     -- Double height font type control byte, not selected
                                    1 downto 0=>"01",   -- Select Instruction table1
                                    others=>'0' -- for bits 6,7
                                    );

However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE:

Type std_ulogic does not match with a string litteral

Any solution to avoid using the equivalent

1=>'0',
0=>'1',

and to allow me to set bits by block?

Best Answer

The assignment X downto Y => 'A' is correct when A is a element of array. For example, this snippet is correct:

1 downto 0 => '1',

And this snippet is wrong:

1 downto 0 => "01",

Therefore, your assignment is illegal. As your code, you can assign as:

DataOut <= (                        5 downto 3 =>'1',     
                                    2 downto 1 =>'0',     
                                    0 => '1',  
                                    others=>'0' 
                                    );

If you want to access/assign by a feild of array, you can use concatenation:

DataOut <= Something_0 & Something_1 & "01";

While Something_* is std_logic_vector

Related Solutions

VHDL – Problem with std_logic_vector

One of the features of VHDL is that very little functionality is provided in the base language itself. Most of it is provided by using packages. The second line of your code is an example of this (use ieee.std_logic_1164.all). This means that you are using all of the std_logic_1164 package. See here for what this package defines.

When you write code, you generally want to store your signals in either std_logic or std_logic_vector. There are two reasons for this. The first is that a std_logic can also represent values other than '0' or '1'. It can also represent 'Z' or 'X' for example. The second is that the simulators (such as modelsim that you are using) are optimised to run faster with std_logic.

As a general convention, it is good practice to always make the inputs and outputs from your entity a std_logic or std_logic_vector.

The specific problem you are having is that you are using the type bit (which is one of the very few types defined in the VHDL standard) with xor.

The simplest solution is to change the co output in your entity to be of type std_logic and to change the declaration for sum and cin to be of type std_logic.

entity binadder is
    port(n,clk,sh:in bit;
         x,y:inout std_logic_vector(3 downto 0);
         co:inout std_logic;
         done:out bit);
end binadder;

    signal sum,cin:std_logic;

A further comment is that it is generally bad practice to make your ports inout unless you have a very good reason to do so as this removes some of the strict type checking that is built into the language. The best solution is to create a signal within the entity itself and assign the signal directly to the output.

entity binadder is
    port(n,clk,sh:in bit;
         x,y:inout std_logic_vector(3 downto 0);
         co:out std_logic;
         done:out bit);
end binadder;

    signal co_int:std_logic;
 begin
    co_int<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
    co <= co_int;

One final comment is that once the value of state is 1, how will it ever become 2 or 3?

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)

In principle, the representation of a VHDL integer is undefined.

In practice, you can normally assume that a synthesis tool will use a 2's complement representation, taking into account the range constraint. Therefore, the relation between the range constraint and the implemented bit width is straightforward, even though reporting the bit width from within VHDL is not.

Best Answer

Related Solutions

VHDL – Problem with std_logic_vector

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)

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