Adder hardware logic

digital-logic

schematic

simulate this circuit – Schematic created using CircuitLab

If this circuit is a part of a 4 bit full adder, where A1,B1 are adder inputs and C1 is carry in from previous bit, does C2 give the correct output for the carry out bit? According to my calculations C2 doesnot, although S1 generates the correct value of the sum. Please, I need a cross-check.

Best Answer

This circuit is more complicated than necessary, but it looks like C2 does give the correct output. The simplified expression for C2 is: $$ C_2 = \overline{\overline{(A_1+B_1)}+(\overline{C_1} \cdot \overline{A_1B_1})}\\ =(A_1+B_1)\overline{(\overline{C_1}\cdot\overline{A_1B_1})}\\ =(A_1+B_1)(C_1+A_1B_1)\\ =C_1A_1+C_1B_1+A_1A_1B_1+A_1B_1B_1\\ = C_1A_1 + C_1B_1 + A_1B_1 $$