AN7149N -based power amp usage

There are known effects like this that need to be taken into account for high precision circuits. Thermal gradients can also have adverse effects, component orientation across or along stress and thermal gradients etc.

Of course we have to do some guessing because we can't magically know what is in the package. But an educated guess is that the die is either eutectic bonded or glued very rigidly to the bottom of the package cavity. A small SOIC package is very non compliant (i.e. rigid) so the stresses translate directly into the package die cavity floor and then through the die attach into the Si substrate. Stress can adversely affect Si performance by affecting the electron/hole mobility and Si has known piezo resistance (through similar effects of lattice changes).

In fact Intel uses localized stress to increase the performance of PMOS transistors at some process nodes. In laying out precision circuits in silico it is recommended that sensitive amplifiers in Si not have metal layers over them so that the transistors are not adversely affected. (but here it is a matching issue).

to test the hypothesis: I recommend desoldering the amplifier, and then attaching short stubs of PTH (resistor would work) leads to lift the package up off the PCB so the stress doesn't translate into the package. Once you've fiddled with this and re-fired it up. You should see a change and therefore a verification. USe the new "legs" as compliant members. Or use solder braid if you want to get really carried away.

Solutions? a DIP version of the same part will have less of an issue because the leads are compliant. In that case using a compliant thermal compound under the package to get heat out might be used.

You should also consider your board design as a contributing factor. Perhaps running stiffeners (in the existing design) as a test will help eliminate/study the issue. I'd epoxy stiffer pieces of FR4 (on edge) just to see.

You do realize, I hope, that the problem is that you're overdriving the inputs, right? and that a diode network will not prevent that, just make the results a little less nasty? And that the real solution is not to ask for too much output from the board?

OK, so you want to do it anyway. I hope you've got good eyesight and a steady hand.

Looking at the PCB screenshot, the input connector is the 3-pin connector at the upper left. The signals are carried on the upper and lower pins, while the center pin is ground. You can see the two signal traces going right and down to your 2 capacitors just under the 5-pin IC. The right-hand pad of each capacitor is where you want to make your connection.

Good luck.