Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp
and data2_temp
to be declared as reg
's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.
If you want to capture these values in actual registers, you need to add those explicitly:
reg [7:0] data1, data2;
always @(posedge someclock) begin
data1 <= data1_tmp;
data2 <= data2_tmp;
end
But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.
You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg
doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk)
then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.
I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?
You need a clock to update a (physical) register. You can read it out at any time. For example:
wire [8:0] sum;
assign sum = k0 + k1;
is perfectly valid code. sum
will change whenever any of its inputs changes. If k0
and k1
are the outputs of flip-flops, their values will only change when there is a clock edge.
For another example, you could equally well describe your multiplexers with code like this:
reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
(reg1 == 1) ? k1 :
(reg1 == 2) ? k2 : k3;
how do I read from this tag_array and do the comparison all within the same clock cycle?
Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.
RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.
I got confused because frankly I don't know enough about memory hardware and how that's possible.
Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.
You'll need to use the clock to break up the write and read operations. Here is an example of a test bench that writes data to two addresses then reads them back.
wire [DATA_WIDTH-1:0] data = we ? wdata : {DATA_WIDTH{1'bz}}; // tri-state write output driver
ram i_ram0(clk,we,addr,data);
initial begin
clk = 1'b1;
data1 = 'h0F;
data2 = 'hF0;
addr1 = 0;
addr2 = 2;
we = 1'b1;
addr = addr1;
wdata = data1;
@(posedge clk) #1;
addr = addr2;
wdata = data2;
@(posedge clk) #1;
we = 1'b0;
addr = addr1;
@(posedge clk) #1;
if(data !== data1) $display("ERROR data:%h != data1:%h @ addr:%h", data,data1,addr);
addr = addr2;
@(posedge clk) #1;
if(data !== data2) $display("ERROR data:%h != data2:%h @ addr:%h", data,data2,addr);
@(posedge clk) #1;
$finish;
end
FLY if data
is an inout
, then you need a tri-state driver in your ram module:
assign data = we ? {DATA_WIDTH{1'bz}} : rdata; // tri-state read output driver
Full working example here: http://www.edaplayground.com/s/6/221
Best Answer
A physical memory has a fixed number of read (and write) ports. If you want to search for a value inside the RAM, you would need to read every entry. So either you have enough ports to read them all in parallel, or you need to iterate using the read ports you have over multiple cycles.
Really, you need to google CAM (content-addressable memory), that's what you are trying to build, and they are not built from standard memory blocks.
Among other issues in your code: your memory doesn't seem to actually respond to read requests (nothing is driving read_data), so no wonder you get don't care results.