Convert C to FPGA

fpgaisevhdlvivado

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator.

Problem is, there are tons of information out there and almost all good programs need an expensive license.

I'm going to be given a Xilinx FPGA (probably a Virtex-6) and so I will have a valid license to use Vivado HLS and ISE. So now, my idea on how to convert a C algorithm to the FPGA is this:

1 – Convert the algorithm from C to VHDL and optimize with Vivado HLS (already understood from tutorials how to do this step)

2 – Use the newly generated VHDL files in ISE to generate a bitstream (no idea how to do this)

3 – Use the Xillybus to connect a C program with the FPGA (with the bitstream) and send/receive information to be able to see the outputs.

Am I on the right way and am I lacking some step? About step 2, it is straigh-forward to generate the bitstream in ISE or to I need a lot of knowledge about port-forwarding?

Best Answer

Answering your comment question here where I have more space. Let's say you have an application you've designed on a linux box, and it runs an algorithm you wrote for counting the number of cat pictures on the internet. Now it runs but it's slow because there is a lot of cat pictures to go through, so you want to accelerate it in hardware.

So you use this tool to write OpenCL code which is in C but with some restrictions on form because it's going to be "compiled" to run on an FPGA. The call this portion of the code kernels. Now these kernels are going to be synthesized and run on the FPGA, maybe you have 1 or maybe you have a 100 working parallel.

You're doing all this right in your application, inline, so when you get to the point of actually counting the cats you're using their APIs to do the processing on the FPGA.

I just saw your other comment that it's not out yet, I know Altera's stuff has been out for a while you can find a bunch of design examples here

All that said it depends what your goal here is, do you want to learn how to write verilog, test benches, and be an FPGA designer? Or are you looking to just accelerate algorithms or functions using hardware without doing all that?

Like any tool-set, which one to use depends on the job at hand.

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Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Drive electo-optic modulators with FPGA

While I may have misunderstood your drive requirements, a MOSFET gate driver would seem to be a good place to start. TI makes a line http://www.ti.com/lsds/ti/power-management/gate-driver-products.page#p9=3.2;5.3&p528=4;6&p529=12;14&p248=1;7.6&p598=TTL and a UCC27611 seems a decent choice. 5 nsec rise and fall times, and 10 volts into 50 ohms is .2 amps, while the IC will do .3 amps average. It comes in a very small package, too. And lots of other manufacturers make something similar, so I'm not specifically recommending this one, just using it as an example.

Best Answer

Related Solutions

Electronic – Pipelining and clock frequency issue

Drive electo-optic modulators with FPGA

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