Electrical – Are DDR3 SDRAM’s DQL and DQU pins different

There are no real downsides to any impedance for EMI, as long as you have matched impedances on source, termination and trace.

One thing that many fail to consider is the typical routing of DDR2/3 with a data line that goes far enough from the CPU to be considered a transmission line, then T's to go to each chip (or 4 chips, etc.) The 50 ohm impedance just dropped to 25 ohm, with two traces in parallel. This creates an impedance mismatch, which always creates a reflected signal and noise on the line.

The proper way to handle this is to T the lines either close enough to the CPU to still be considered a lumped length, with a series termination at the T of 1/2 the line impedance. The signal sees 25 ohm resistor to a 25 ohm parallel set of 50 ohm transmission lines and everything is good. Or this can be done where the T's will be short enough to be considered lumped at the two RAM chips.

A similar setup can be used to match impedances differing CPU to RAM, but it is best to keep SoC and RAM source and termination impedances the same, then make traces to match.

If you have differing impedance only at the RAM side, you should be able to use parallel or series termination resistors to match to that.

As already noted, you should definitely have terminations to Vtt (0.75V for standard DDR3). This source must be able to both sink and source current. There are regulators available for this specific task.

The address and control group should be DC terminated (I used 40.2 ohm parts) and the clock pair should be ac terminated (clock and complement each with 40 ohm resistors, both tied to a 100nF cap which then goes to Vtt).

Note that there are many register settings that control DDR3 memory interfaces, and you have to be careful to get them all correct.

Micron remains a wonderful source of information on using DDR3 as well as anything else they make.