Electrical – Circuit diagram of synchronous sequential circuit using rising edge triggered D-type flip-flops

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How do I draw a circuit diagram for this system using the "one flip-flop per state" technique?Timing diagram

UPDATE:

This is what I have so far, but I'm getting so confused.

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Best Answer

The first step toward implementing a state machine is to draw the state diagram that it will implement. A state diagram shows every state that the machine can be in, along with all of the conditions that cause it to switch from one state to another (or not).

A timing diagram is actually an incomplete specification for a state machine, because it does not cover all of the possible combinations of current state and inputs. This means that you can come up with one possible answer, but there may be others. In this case, you should pick the simplest answer that meets the requirements.

The outputs are simple; we can see that OUT1 corresponds to state B and OUT2 corresponds to state D.

In the given timing diagram we see the following transitions:

  • A → A when IN1 = 0 and IN2 = X
  • A → B when IN1 = 1 and IN2 = 0
  • B → C when IN1 = 0 and IN2 = 0
  • C → A when IN1 = 0 and IN2 = 0
  • B → D when IN1 = 1 and IN2 = 0
  • D → D when IN1 = 0 and IN2 = 0
  • D → A when IN1 = 0 and IN2 = 1

The following combinations are unspecified:

  • state A when IN1 = 1 and IN2 = 1
  • state B when IN1 = 0 and IN2 = 1
  • state B when IN1 = 1 and IN2 = 1
  • state C when IN1 = 1 and IN2 = 0
  • state C when IN1 = 0 and IN2 = 1
  • state C when IN1 = 1 and IN2 = 1
  • state D when IN1 = 1 and IN2 = 0
  • state D when IN1 = 1 and IN2 = 1

One interpretation is to assume that the unspecified combinations do not cause state transitions.

Other interpretations are possible — for example,

  • We could assume that IN2 is a "reset" input, because in all cases when it is asserted, the next state is A.
  • We might also assume that state C always makes the transition to state A, because we never see it do anything else.
  • That just leaves the case for state D when IN1 = 1 and IN2 = 0 — I would be inclined to leave it in state D. It's my impression that state D (and OUT2) is intended to "latch" pulses on IN1 that are two or more clocks wide.

Together, these assumptions cover all of the unspecified transitions.

Only after you have a complete state diagram can you start designing the logic for an implementation. The nice thing about "one-hot" designs (one FF per state) is that the logic pretty much follows the state diagram one-for-one.

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