(From Schuam's Outlines Computer Architecture, 2002, page 193, problem 8.7(b))
Suppose I have the following memory hierarchy of:
CPU <-> SRAM <=> DRAM <=> DISK
SRAM has 5 ns access time
DRAM has 60 ns access time
DISK has 7 ms access time.
If the hit rate at each level of memory hierarchy is 80% (Except the last level of DISK which is 100% hit rate), what is the average memory access time from the CPU?
So I start the problem… here are my calculations:
For the DRAM Level the access time is:
$$
T_{DRAM} = (0.8)(60 ns) + (0.2)(7 ms)
$$
$$
T_{DRAM} = 1.448 \mu seconds
$$
For the SRAM/CPU Level the access time is:
$$
T_{SRAM} = (0.8)(5 ns) + (0.2)(1.448 \mu s)
$$
$$
T_{SRAM} = 293.6 ns
$$
Now for the problem, the solution manual for the book says the answer is:
$$
T_{SRAM} = (0.80)(5 ns) + (0.20)(0.80)(60 ns) + (0.20)(7 ms)
$$
which I calculate to be: 1.4136E-6 seconds and they calculate to be:
$$
T_{SRAM} = 280,0136.6 ns
$$
My answer is "293.6 ns", and the book's solution to the problem is "280,0136.6 ns"
Who is right and why?
Best Answer
Your formulas look fine to me, but there's an error in the numbers: $$ T_{DRAM} = (0.8)(60 ns) + (0.2)(7 ms) \\ T_{DRAM} = 1.448 \mu s $$ This is incorrect, with \$0.2 * 7\$ ms in the sum, the answer should be at least 1.4 ms, not µs.
Note that 1 ms = 1000 µs = 1 000 000 ns.
Compare:
$$ T_{DRAM} = (0.8)(60 ns) + (0.2)(7000 ns) \\ T_{SRAM} = (0.8)(5 ns) + (0.2)(T_{DRAM}) \\ T_{SRAM} = 293.6 ns $$
with:
$$ T_{DRAM} = (0.8)(60 ns) + (0.2)(7000000 ns) \\ T_{SRAM} = (0.8)(5 ns) + (0.2)(T_{DRAM}) \\ T_{SRAM} = 280013.6 ns $$
If you substitute \$T_{DRAM}\$ in the \$T_{SRAM}\$ expression, you get:
$$ T_{SRAM} = (0.8)(5 ns) + (0.2)(0.8)(60 ns) + (0.2)(0.2)(7000000 ns) $$
The expression you quoted from the book is slightly different (only one \$(0.2)\$ in the last term of the sum). That looks like either an error in the book, or in your quote.