Electrical – Error when creating a task in separate file in verilog

hdlverilog

module tb();

    reg [7:0] a = 1;
    reg [7:0] b;

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask


endmodule

The above code is compiled and simulated correctly; But I want to cut the task "AddTask" from the module "tb.v" and place it in a separate module "AddModule.v"(that is in a separate file) for clear coding. When I do this, modelsim can compile it but can't simulate it and give the error:
" Unresolved reference to 'AddTask' ". Although I include AddModule.v, it can't recognize AddTask. Can you help me please, what's the wrong ?

module tb;

    reg [7:0] a = 1;
    reg [7:0] b;

    `include "AddModule.v"

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end
 endmodule

AddTask in a separate file:

module AddModule;

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask

endmodule

Best Answer

The problem is probably the nested module declaration. This is not allowed in Verilog, however is possible in SystemVerilog.
Try to declare only the task AddModule() in a separate file without a surounding module declaration. This file can then be included within the scope of another module, e.g. within your testbench (as in your example code).

Related Solutions

Task in verilog code

The issue could be stemming from the fact that you don't have any delays in the verilog code under the for loop (including the code included in the tasks). There could be multiple driver issue.

You can try adding #1 in your for loop and see if that helps.

I notice that the question is pretty old. Might be useful for future exchangers.

Test_bench in Verilog using Task

It would be helpful if you could clarify this statement :

How should I define input in argument in task so that input should be given independently?

A task defined as:

task display_redux
  input [31:0] a_number;
  begin
    $display("display_redux was sent : %d", a_number);
  end
endtask

Can be called with :

display_redux(20);
integer ii = 6;
display_redux(ii);

To me the input here is independent from anything else, and you can not assign value to the input so it does not have side effects from of modifying inputs from where it was called.

Taking one of your tasks:

task exp_case_2b
  input data_i;
  input reset;
  input read;
  input dcsel;
  input xlat;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb);
  end 
endtask

Youve declared many inputs which you are not driving when you call it with exp_case_2b(data_out). You have defined inputs then are trying to drive values on to them. You need these to be regs and not inputs so they are local to the task. Or not defined at all and use hierarchical references to the top level reset, aka tb.reset = 0;.

I think this might have been what you were trying todo:

task exp_case_2b
  input      [47:0] data_i;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb); //No idea where this variable comes from
  end 
endtask

Then call :

 exp_case_2a(data_i_t, data_out_1);

AddTask in a separate file:

Best Answer

Related Solutions

Task in verilog code

Test_bench in Verilog using Task

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