Electrical – FPGA – What is the maximum allowed DRAM capacity on an XUPV5-LX110T Development Board

No fundamental reason why not. Synchronous SRAM is truly random access, fairly inexpensive, and easy to interface to.

Its downside in that it occupies a fairly narrow niche between the on-chip BlockRam (not much smaller, free until it forces you to select a larger chip, massively parallel and more flexible) and external DRAM (massive storage capacity at a price SSRAM can't match).

So up to 0.5 or 1MB, external SSRAM is unnecessary, and above 8MB or 16MB (numbers may vary according to your budget and current prices!), SSRAM becomes expensive enough that DRAM takes over despite its limits. Then - if you need random access - you have to massively reorganise the computation to read chunks (bursts or pages) from DRAM into BlockRam where you can process it fast before writing back bursts etc....

But if you have a role for SSRAM within that window, go for it. I have added simple home-made SSRAM boards to augment commercial FPGA platforms where necessary.

Dual port block RAM and LUT RAM is pretty much impossible to beat as it is on the FPGA die and accessing it does not require using any I/O pins. If you don't have enough capacity in block RAM, then you can throw external memory at the problem. QDR SRAM is dual ported and so has double the bandwidth of SDRAM, this can be useful for some applications, though it is very expensive. DDR3 SDRAM is probably the cheapest option, but even this is relatively slow compared to what you can do with LUT RAM and block RAM.

I think you're going about your design the wrong way. Besides, if you need to do any real processing on that many inputs, the logic alone would consume an absolutely gigantic amount of area, and may not fit on the largest FPGAs available today. What FPGAs excel at are very high speed pipelined processing operations. What you should do is figure out how many pixels per second you need to process (640x480xfps) and then figure out how to implement your image processing algorithm to get that level of performance. Generally the idea is to read in a small number of pixels per clock cycle and then process them in an orderly fashion.