Electronic – External clock with Arty Z7 FPGA development board

fpgaxilinxzynq

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same.

Is there an input on the Arty Z7 board that works as an external clock? If not, is there a dev board for zynq that does? Any pointers to how to configure that in the vhdl?

Update: maximum sample rate is 384Khz. maximum bits per channel is 32. maximum channels is two. Consequently, maximum clock is 24MHz. Max z7 clock is ~100Mhz? I do not believe that this is a high enough multiple to avoid clock inaccuracies on the output (but would be happy to be wrong). This is an audiophile application and avoiding jitter is very important.

Best Answer

Yes, there are pins available on the Arty Z7 that can be used as native clock inputs to the PL fabric. Page 9 of the schematic shows the pin names in each of the banks of the PL used in the design. This Xilinx Forums question about SRCC and MRCC pins gets to the necessary information: the pins labeled SRCC and MRCC are clock input capable pins, some of which are routed directly to user-facing pins on the Arty Z7.

Since you're after external IO, you'll probably use the PMOD or Arduino headers on the Arty Z7. The PMOD pins are prefixed with JA and JB while the Arduino headers use the prefix CK_IO. Assuming single-ended clock inputs for your I2S-like implementation, you have these pins available:

IO_L11P_T1_SRCC_13/U7 - CK_IO29
IO_L13P_T2_MRCC_13/Y7 - CK_IO37
IO_L14P_T2_SRCC_13/Y9 - CK_IO41
IO_L12P_T1_MRCC_34/U18 - JA3_P

Of course, other boards will have similar IO features. Depending on your FPGA fabric, processor, and IO needs, a different board will be an option.

For more details from Xilinx, see:

UG472 (v1.14) July 30, 2018 section "Clock-Capable Inputs" pg 30 and onward, explaining how to use these inputs
UG475 (v1.18) July 16, 2019 "Table 1-12: 7-Series FPGAs Pin Definitions (Cont’d), Other Pins" pg 30-31 providing the definitions for the pin name abbreviations

As for configuring this in VHDL, you'll be using this as one of the clock domains in your design. Your pin assignment constraints will need to place the input clock pin in the correct location given the above information and your choice of how you're connecting. As for the design, it will depend on whether or not your clock input and output rates are constant or dynamic and continuous or discontinuous. If you're looking for the most flexibility, I would suggest having a constant-clock resampler/custom-DSP running on one of the board clocks with FIFOs to/from the different precise and ratio-frequency IO domains.

Related Solutions

Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Electronic – Generate an 40MHz Clock on an FPGA with 100Mhz clock

The simple prescaler you've implemented follows the formula $$ fout = fMaster \div (2 * (1 + prescalerN)) $$ where fMaster is the 100MHz master clock input and prescalerN is the prescaler reload value. There's not a whole-number divisor of (100MHz/2) that produces 40MHz. This is a limitation of implementing the prescaler in general-purpose programmable logic.

Many FPGA include specialized clock generation blocks such as PLL (Phase-Locked Loop). This is a specialized analog circuit implemented in FPGA silicon, which can be configured to run at a faster internal clock than the applied master clock. So the external 100MHz clock might be doubled to 200MHz or maybe up to 400MHz. The PLL uses a control loop principlie similar to what an op amp uses, to accomplish generating a stable higher internal frequency, from a stable lower frequency external reference.

Some Xilinx FPGA have DCM (Digital Clock Manager). Altera calls this kind of thing a "megafunction" if I remember correctly, there should be a megafunction for PLL. Depends on exactly what FPGA you are using. Consult the FPGA's main data sheet.

Best Answer

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Electronic – Pipelining and clock frequency issue

Electronic – Generate an 40MHz Clock on an FPGA with 100Mhz clock

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