Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
Electrical – How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop
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Related Solutions
You mention Altera so I assume this is an FPGA design.
If this really is the ideal case (you're ignoring the wire delays due to physical location of the elements) then yes, ideal tCOmin is 3ns. This is the best case (shortest delay, fastest clock) under ideal conditions.
However, post-synthesis simulation will reveal a more meaningful result once the circuit elements have been mapped to specific flip-flops at specific locations on the FPGA. This constrains the available wiring routes, which is where the wiring propagation delay is determined. For a large FPGA chip with high utilization, it becomes more likey that placement is not ideal. Since the worst (longest) tCOmin total delay is what constrains how fast the system can be clocked, the synthesis tools analyze the whole FPGA system and report on whichever circuit has the worst tCOmin, so that the designer can focus their efforts to make a large system perform as required.
The diagrams below with the setup and hold requirement inequalities, illustrate how clock skew helps or hurts meeting hold or setup
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Best Answer
An async reset doesn't have a setup or hold time. Setup and hold are relative to a clock, an async input doesn't use a clock.
It will have a minimum active time, a propagation delay before the reset is reflected in the outputs and also a minimum idle time after being released. i.e. If you get a clock edge at exactly the time the reset goes away does it count as a clock or are you still in reset?
A sync. input will always have setup and hold times. For a reset these may be the same as for the data inputs or they may be different.
As with any timing, what happens when you violate the reset timing is undefined. It may reset, it may not reset or it could (and this is a long shot) change to some other non-reset state.