digital-logiclatchlatchingpower electronicsrace condition
I have designed an SR latch using Cd4001 NOR gate IC. When both S and R are low the circuit refuses to stay in previous state even though I am using appropriate dropping resistors. Is there any way to avoid this with same CD4001 circuit configuration.
This is the circuit configuration i am using:
First a slight correction to your diagram. The NOT Q output is the output of the NOR1 gate, not the input you have shown.
When both inputs are LOW (0) the latch holds it state.
With S, R = 0, 0
If Q = 1, then NOR1 input is 0,1 and its output (NOT Q) is 0 keeping Q = 1 If Q = 0, then NOR1 input is 0,0 and its output (NOT Q) is 1 keeping Q = 0
i.e. NO CHANGE
If S = 1 (R = 0) then the output of NOR1 (NOT Q) will be 0 and the output of NOR2 (Q) will be 1 - the latch is SET, Q is HIGH
If R = 1 (S = 0) then the output of NOR2 (Q) will be 0 and the output of NOR1 (NOT Q) will be 1 - the latch is RESET, Q is LOW
The problem comes when both S and R inputs are taken HIGH at the same time and forms a race condition. This logical condition (S = 1, R = 1) is to be avoided as the output cannot be determined.
The problem is the PN junction from the base to collector or T4. When T5 is off, the emitter of T4 is floating. If you now apply a high voltage to the left end of R5, T4 acts like a diode from base to collector. This turns on T6 directly from the high output of T3.
Put another way, the NAND gate formed by T4 and T5 has a bug. It doesn't work when the T4 input is high and the T5 input low. Your overall logic was right, but due to T5 being off, T4 doesn't work like the transistor you are assuming anymore.
To make a NAND gate, just flip your NOR gate around using PNP instead of NPN:
By the way, this whole problem goes away if you use logic-level N-channel MOSFETS instead of NPN transistors. You can stack those and get what you intended.
Best Answer
Attaching LEDs like that to a little CD4001 is drawing too much current from the output when powered from only 6V. You are pulling ~8mA and the device is only rated for closer to ~2mA.
What will happen with that type of SR latch is the high output will be pulled down to close to the threshold level of the other gate and it will switch and settle to whatever side is less strained, or it might oscillate.
You should reduce the load, or change the way the LEDs are driven. One possibility is to use the other two NORS in that package as a buffer.
simulate this circuit – Schematic created using CircuitLab
But you will still be straining the outputs.
Also make sure you have decoupling capacitors on that chip.