bufferdecodertri-state
Suppose that AB and CD are 2-bit unsigned binary numbers
(a) Find the truth table for the function F with 4 inputs A, B, C, D to satisfy the following condition
if AB >= CD, then F = 1, otherwise F = 0
(b) implement 8×1 multiplexer using 3×8 decoder and 3-state buffers
Am I right?
The function can implemented using only the 74LS138. Look at the data sheet (for example at http://www.alldatasheet.com/datasheet-pdf/pdf/51039/FAIRCHILD/74LS138.html , truth table and logic diagram on page 2). The pins are G1, G2A, G2B, A, B, C, Y0, ... Y7. Functionality it can be described as:
Y[7:0] = (!G1 || G2A || G2B) ? 8'hFF : ~(1'b1 << {C,B,A})There are may possible solutions. Pick a Y pin and choose an input configuration that matches your function. For example: A and B pins will connect to the corresponding names from your function. Set G1 high, G2A low, and G2B low. If C is set to low, then F will be Y3. If C is set to high, then F will be Y7.
First let's see how to implement a function using single decoder. It is a straight-forward task having the truth table. Decoder will output 1 on the lines selected by the input, so if we just "or" the outputs corresponding to the truth table lines with X=1, we will get the exact required function:
Unfortunately there is no straightforward way to convert it to 2->4 decoders. But maybe we can divide the original function to smaller ones, suitable for 2->4 representation? Let's look at it. After some manipulations I've omitted here, the function can be represented as $$A_1B_1'+A_0B_0'(B_1'+A_1)$$
So we can see here three different 2-variable functions combined with ANDs and ORs:
1) \$A_1B_1'\$
2) \$A_0B_0'\$
3) \$B_1'+A_1\$
while (1) and (3) are functions of the same variables and can share decoder.
So the solution would be: Implement functions (1)-(3) using the method above, and interconnect the outputs using the gates:
Best Answer
a) You are wrong. Your truth table has several wrong entries, e.g. 0001 should be 0, not 1.
b) The drawn in OR gate though is wrong. With all but one input floating it is anyones guess what the output of an OR gate would be. Simply connect all the outputs together without further logic.
c) Your idea of connecting 1 and NOT D input signals to the 3-state buffers though is right. Except your bad truth table makes the result wrong. You also need 0 input for some.