Via impedance can be approximated by its capacitance and inductance. From pages 257 to 259 of High-Speed Digital Design:
$$ C_{\text{via}} \text{[pF]}=\frac{1.41 \epsilon_r T D_1}{D_2-D_1} $$
D1: diameter of pad surround via [in.]
D2: diameter of clearance hold in ground plane(s) [in.]
T: thickness of PCB [in.]
\$\epsilon_r\$: relative electric permeability of circuit board material
The 10%-90% rise time degradation for a 50\$\Omega\$ transmission line due to this capacitance will be \$ {T_{10-90}}=2.2C_{\text{via}}(Z_0/2)\$.
$$ L_{\text{via}} \text{[nH]}=5.08h\left[ln\left(\frac{4h}{d}\right)+1\right] $$
h: length of via [in.]
d: diameter of via [in.]
Inductive reactance is \$ X_L \text{[}\Omega\text{]}=\pi L_{\text{via}}/T_{10-90} \$. I'll leave making the link between XL and T10-90 degradation to someone who has actually done this.
Total via delay is estimated in the sequel, High-Speed Signal Propagation, on pages 341 to 359, to within an order of magnitude, with the following comment:
It makes no sense to define, or to attempt to measure, the inductance of a via without also specifying how the attached traces bring current through it, and how the planes carry the returning signal current.
$$ t_v=\sqrt{L_VC_V} $$
LV: incremental series inductance
CV: incremental shunt capacitance
To properly measure [CV], first measure the static capacitance to the reference planes of a configuration that includes an input trance of length x, the via, and an output trance of length y, where both x and y greatly exceed the clearance-hole diameter. The lengths x and y are measured to the center of the drilled via hole. Then separately measure the static capacitance of a similar trace of length x + y (with no via and no clearance hole). [CV]... is the difference between your two measurements.
[LV] is defined similarly, but with each trace shorted to the reference plane at its far end. Arrange your equipment to detect the loop inductance of the path entering trace [x where it is shorted] ..., passing through the short-circuit at the far end of [y]..., and returning through the reference planes to the equipment, [where x is shorted].
The pi model can be applied for a more accurate model. Place half of CV in each cap and the full LV in the inductor. These approximations are only good for frequencies above the onset of the skin effect -- at least 10MHz and preferably 100MHz.
If your via is so large compared to the signal risetime that you require anything more than a simple pi-model for the via, then it probably isn't going to work very well for a digital application. Use a smaller via.
I love to use the Saturn PCB toolkit for this kind of calculations nightmare. It does everything ! (except the coffee.)
Try it. For your inductor (28nH) I get roughly
- 3 turns
- 0.2mm conductor spacing
- 0.2mm conductor width
- 3.320mm outer diameter
- 1.320mm inner diameter
=>28.08nH
I tried to play a little bit with conductors width and spacing value, and from what I see the inductor will not be that sensible to manufacturing defect. For example, reducing the trace width to 0.14mm and raising the spacing to 0.32mm still gives a 26.1nH impedance, which is 'in tolerance'.
But, these kind of components are like PCB antennas and should be tweaked. You can add additional 'feeding' traces to the "prototypes designs" around the first spires and cut them until you come close to the required value (best RLC Q), or scratch the soldermask and solder a wire, or...
Keep in mind planar inductors are cheap in the long run (for big series of cheap product) but cost a lot of time during design due to tuning nightmare and tolerances checking craziness.
But imho it's doable !
Best Answer
Look under "Setup > Cross-section...". In Allegro Free Physical Viewer 16.6 (and 17.2, IIRC), the cross-section report lists the layers with name, material, thickness, dielectric constant, loss tangent, etc.
If you have access to Allegro Physical Viewer Plus, it shows a much prettier graphical stackup representation, but it is still the same information, just displayed differently.