Electrical – LVDS signal to FPGA

Were you trying to assign those pins as outputs? Xilinx Spartan3 FPGAs have a restriction that the differential standard outputs can be assigned to Banks 0 or 2 only. Only a few combinations of IOSTANDARDS are also possible on those banks. For further details, please refer to Differential I/O Standard Bank Compatibility" section under chapter 10 in UG331.

Not sure why the differential standard is not showing up in the "Create IO Ports" option in PlanAhead. However, if you want to assign it through .ucf, you can use this syntax:

NET LOC = | IOSTANDARD = LVDS_25; NET LOC = | IOSTANDARD = LVDS_25;

This example is assuming that you are trying to use 2.5V LVDS IOs. If you are trying to use another IOSTANDARD, please substitute the keyword for the respective standard.

You can't properly describe an LVDS receiver or transmitter in VHDL. LVDS interfaces have electrical requirements that typically cannot be met by just using plain digital input and output pins. Your FPGA needs to have dedicated input and output macrocells for those functions and you would just instantiate them. Exactly how that is done depends on the exact FPGA and toolset you are using. Within the FPGA, there is just one signal that would come from the LVDS receiver and one signal that would go to the LVDS transmitter.