Electrical – Maximum frequency FPGA

fpgafrequency

I need to design a component and choose on which FPGA i will implement it.

One module of the FPGA will be synchronous of a signal TXCLK that is generated by an external component the LM98640 and the frequency of TXCLK is about 640 MHz.

I've read the datasheets but i'm not sure which parameter i should check to be sure that the FPGA can work with signals as fast a 640 Mhz

I'm aware that the way i design it will affect the maximum operating frequency, but i'm looking for the values for each FPGA in case the design is really simple of maximum frequency.

I'm confused between Digital Frequency Synthesizer (DFS) or Delay-Locked Loop (DLL) or GTP transceiver clock ?

Thank you

Best Answer

Xilinx's, for example, have very fast giga-bit transceivers that can operate at multi-gigabit/sec rates, but they also have simple serial and parallel shift registers out at the IO edges of their dies that are typically used for the serial to parallel shifting in both directions. In addition, to get the fastest speeds with synchronous external clocks, I typically use half-rate clocks and DDR (double datarate serializer or de-serializer settings). Its pretty straightfoward in a series-7 Xilinx to get 1Gb/sec on each LVDS I/O pin when applying a 500Mhz external clock. This is all done without using the gigabit transceivers. This also involves no PLLs so it can operate smoothly from low speeds to high speeds continuously.

If you have 640MHz clock today, you may be after 640Mbps on your data lines. My recommendation would be to use a 320Mhz clock and a 1:4 or 4:1 internal serial-to-parallel or parallel-to-serial converter in DDR mode (See Xilinx OSERDESE2 and ISERDESE2 built-in components). This would leave your parallel clocking rates in your main logic down at 160Mhz which is OK.

There are good application notes on setting this up. You can also use the built-in IP features of their development tools to create this component for you.

Hope that helps.

Related Solutions

Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Electronic – Unexpected Verilog warning re FPGA clock assignment

The warning is basically suggesting that you use an explicit clock primitive, which for whatever reason isn't inferred automatically by the tools.

There should be a reference for your particular FPGA that tells what primitives are available. For a Spartan3E, for example, Xilinx UG617 describes the BUFGCE primitive ("Global Clock Buffer with Clock Enable") and shows how to instantiate it. Other vendors will have similar documentation.

Your clock distortion is probably occurring because tristating an output line isn't something that can be done instantly. Whatever is being driven has both inductance and capacitance, so even if the driver could go high-Z in zero real time (which it can't), the driven network will continue to ring for some time. If that's a problem, you would need to find a way to ensure that the clock line is low, and has been for some time, before tristating it. All in all, there is probably a better way to accomplish your goal besides tristating a clock.

Best Answer

Related Solutions

Electronic – Pipelining and clock frequency issue

Electronic – Unexpected Verilog warning re FPGA clock assignment

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