I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these verilog stdcells. This ".lib/.db" files have been provided to me by stdcell IP vendor.
I want to run AMS simulation in Cadence Virtuoso environment. However I can't use ".lib" file directly for timing and need to convert it to a SDF format in order to use it inside Cadence ADE.
Does anyone know how can I convert this “.lib” timing file into SDF format using Synopsys primetime or other synopsys tools? (we use synopsys flow for digital).
I'm only interested in IO path delays in SDF file and I want to generate SDF data by cellname where all instances in design will have same delay.
I took a look at primetime user guide but I couldn't find any section where this process is documented.
Thanks in advance.
Best Answer
You need to push your design through the synthesis flow to get path timing information and generate the
SDFfile. Synopsys flow includes Design Compiler (dc_shell) for design entry synthesis. I’d recommend running in topographical mode to incorporate some interconnect delays. You can use thewrite_sdfat the end of the synthesis to generate an SDF file. More accurate timing data can be obtained after place-and-route (PnR) and physical synthesis. You can use Synopsys IC Compiler or IC Compiler II (icc_shelloricc2_shell) for that purpose and generate a post-PnR SDF at the end. Even more sophisticated Static Timing Analysis (STA) can be performed using Synopsys Primetime. You can refer to Synopsys documentations and their respective Reference Methodologies (RMs) available through Synopsys Solvenet.