Using 0.35u technology (VDD= 3.3v, Vt=0.7, Tox = 0.7 nm), I am trying to set the threshold voltage of an inverter to VDD/2.
If I set the width ratio of PMOS/NMOS to 5 (means the Width of PMOS would be 5 times larger than the NMOS) then the threshold voltage at rising edge of input shows a HI skew, but is around VDD/2 at the falling edge.
If I reduce the width ratio to 1 or 1.25 then at the rising edge of input I see a threshold voltage of around VDD/2, but at the falling edge I can see a LO skew.
I tried playing with Width Ratio to get a threshold voltage of around VDD/2 for both rising and falling input edges, but it seems it is impossible. I even looked at the specs of standard inverter cell coming from the foundry and it shows the same behavior.
It seems it is impossible to set the threshold voltage of CMOS inverter to VDD/2 for both rising and falling edge. Am I correct?
Best Answer
No, it is not impossible to set the threshold voltage to be right at half of the supply voltage. Just to be clear, the threshold voltage is defined as the DC input voltage at which the output voltage is equal to VDD/2. It does not necessarily correspond to an exact delay between rise and fall however.
You can easily set the threshold voltage as accurately as you wish by iteration using something like Newtons Method to size one FET vs. the other (or analysis if the FET properties are handy).
But, this may not necessarily create a gate which has equal rise and fall delays or output slopes (although increasing the PMOS size relative to the NMOS, for example, will both increase the threshold voltage and reduce the rise delay).
Usually the most important characteristic is the output delay and slopes for each load, unless you are trying to use the inverter as a comparator or something.
If you want a balanced gate, what I could recommend is to size the transistors for equal slope at the same load. This generally equates to equal delay as well in a single stage logic gate.