Electrical – synthesizable reg assignment + other questions

verilog

I'm at the beginning of learning verilog and some things are unclear.
Also, I'm just looking for synthesizable code.

What are the differences between this types of assignation: Which of them is synthesizable?

 reg [3:0] data_reg = 4'b1; // what kind of assignment is this? blocking, non blocking?

 vs

 reg [3:0]data_reg;
 initial data_reg = 4'b1;  

 vs

 reg [3:0]data_reg;
 initial data_reg <= 4'b1;

Can I assign reg value to a wire, like:

module foo (output wire [3:0] led); 
reg [3:0] data_reg = 4'b1; 
assign led = data_reg; 
endmodule

For the code above I get the following error: ERROR:NgdBuild:604 in ALTIUM and in XILINX ISE I get Using initial value of led since it is never assigned.

Best Answer

In verilog, reg does not represent synthesisable storage, it is more of a software construct in the language - its also used in case statements.

If you want an actual flip-flop, you need to follow this pattern:

always @(posedge clk or negedge reset_n)
if(!reset_n)
data_reg <= 4'b0000;
else data_reg <= data_input;

and, yes, you can assign any wire (output or not) from a reg (combinatorial or sequential).

Wherever you have initial, it is very likely you have something which is not synthesisable. Silicon has no concept of when initial should occur, so with initial you are maybe anticipating an earlier operation (like writing an image to FLASH memory), or relying on an FPGA synthesis flow inserting some reset initialisation for you.

Related Solutions

Electronic – Birectional I/O pin in verilog

Inouts are actually "wire" so you can't use any procedural/sequential assignments (where the left hand side must be a reg). Generally speaking:

input : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.
output : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.
inout : internally or externally must always be type net, can only be connected to a variable net type.

A common approach is to have an "enable" signal for the output of your inout, and to drive to high impedance if the output is not enabled. In your case direction is playing that role.

So try this instead:

module test(
    input  clk,      // The standard clock
    input  direction,  // Direction of io, 1 = set output, 0 = read input
    input  data_in,    // Data to send out when direction is 1
    output data_out,   // Result of input pin when direction is 0
    inout  io_port     // The i/o port to send data through
    );

    reg a, b;    

    assign io_port  = direction ? a : 1'bz;
    assign data_out = b;

    always @ (posedge clk)
    begin
       b <= io_port;
       a <= data_in;
    end

endmodule

The hardware corresponding to the above code would look something like this:

enter image description here

Electronic – Simulation of blocking assignments in always @ blocks

I'm no Verilog guru, but as I understand it (from here http://www.sigasi.com/content/verilogs-major-flaw amongst other places), using blocking assignments to communicate between clocked processes is asking for non-determinism.

Regarding part 2 - As I understand it... if you only use non-blocking assignments when you communicate between processes, you'll get deterministic behaviour across all simulators. The non-determinism of blocking assignments is not a "simulator thing" - it's inherent in the way Verilog works. Changing the order of the processes in the source files (for example) may change the order of the updates and hence the behaviour of the code, even within the same simulator.

Best Answer

Related Solutions

Electronic – Birectional I/O pin in verilog

Electronic – Simulation of blocking assignments in always @ blocks

Related Topic