Electronic – Unspecified I/O Standard value ‘DEFAULT instead of User defined value. But I can also not assign a value

fpgaverilogvivado

So I'm totally new to this and sorry if this is a really basic question which answer is in the error message.
I get the error:
[DRC NSTD-1] Unspecified I/O Standard: 5 out of 25 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards.

I know which pins are at fault but I cannot assign them values directly: assignment to a non-net is not permitted.

I've been trying to fix this for a few hours and I'm quite at a loss.
I don't want to create a tcl file as it says this may damage the board and this board is quite expensive.

Also this happens when combining two modules.
The modules by themselves with the same code run fine.
Thanks in advance!

Best Answer

Thats a wrong conclusion you are leading to , whenever you have designed the verilog/vhdl module in the constraints file you need to provide the following information,

  • Physical constraints -- Pin location constraints, IO Standard of IO pin(you can see the VCCO,VCC_AUX values in case of xilinx fpga similarly you can see for other FPGAs too),Slew constraints, Equalization of IO for high speed transceivers
  • Clock constraints (create_clk constraints)
  • False paths or MCP paths or Max delay paths (CDC)

  • any other constraints

    module top (input nota, input b, output c) ;

example u_example (
  .a (~nota )
 ,.b (b     )
 ,.c (c     )
);

endmodule

    module example (input a, input b, output c); //...definition of module ...// endmodule

Constriants

  • set_property PACKAGE_PIN AM17 [get_ports "nota"] ;
  • set_property PACKAGE_PIN AM16 [get_ports "b"] ;
  • set_property PACKAGE_PIN AM15 [get_ports "c"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "nota"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "b"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "c"] ;
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