Electrical – system verilog 3d array ,cant insert data , what am I doing wrong

verilog

Im trying to implement 2d convolution (8 bits each cell int he convolution so in systemV it's 3d) in system verilog,and I have trouble inserting data into the "result" array, and i dont understand what im doing wrong, this is my code:

module conv2d (
                input clk,
                input logic [7:0] img[3:0][3:0],
                input logic [7:0] kernel[2:0][2:0],
                output logic [7:0] result [4:0][4:0]
                );//#(parameter img_size=16,kernel_size=4)()
int i,j;


always_ff @(posedge clk) begin
    for(i=0;i<5;i++) begin
        for(j=0;j<5;j++) begin
            for(int k=0;k<3;k++) begin
                for(int l=0;l<3;l++) begin
                    if ((i-k > -1)&&(j-l>-1)&&(i-k < 3)&&(j-l < 3))begin
                        result[i][j] <= result[i][j] + kernel[i-k][j-l]*img[k][l];
                    end
                end
            end
        end
    end
end

endmodule

my testbench:

module test; 
logic clk;
logic [7:0] img[3:0][3:0] ;
logic [7:0] kernel[2:0][2:0];
logic [7:0] result[4:0][4:0];
initial begin
    for(int i=0;i<5;i++) begin
        for(int j=0;j<5;j++) begin
            result[i][j]=8'b0;
        end
    end
clk=1'b0;
img[0][0]=8'd1;
img[0][1]=8'd0;
img[0][2]=8'd2;
img[0][3]=8'd0;
img[1][0]=8'd1;
img[1][1]=8'd2;
img[1][2]=8'd3;
img[1][3]=8'd1;
img[2][0]=8'd0;
img[2][1]=8'd0;
img[2][2]=8'd1;
img[2][3]=8'd0;
img[3][0]=8'd1;
img[3][1]=8'd0;
img[3][2]=8'd3;
img[3][3]=8'd1;
kernel[0][0]=8'd1;
kernel[0][1]=8'd0;
kernel[0][2]=8'd0;
kernel[1][0]=8'd0;
kernel[1][1]=8'd1;
kernel[1][2]=8'd0;
kernel[2][0]=8'd1;
kernel[2][1]=8'd1;
kernel[2][2]=8'd0;
end
//#100;
//$stop;
always #5 clk = ~clk; 
conv2d con4test (
                    .clk(clk),
                    .img(img),
                    .kernel(kernel),
                    .result(result)
                    );
endmodule

this is my first time my first time working with system verilog and 3d arrays, couldnt find any helpful info online, dont be harsh with me.

Thanks!

EDIT: fixed the test bench problem.
And my problem is that the result array is not updating meaning it's still 0

EDIT: working!

I did few changed in the code, but the one who did the work (I think) was changing always_ff with always I will tell the truth i have no idea why..
and I'll be super interested if some one knows.

Thanks again.

Best Answer

After some time of debugging and simulation I can say that you must move result initialization into the conv2d module:

module conv2d (
    input clk,
    input logic [7:0] img[3:0][3:0],
    input logic [7:0] kernel[2:0][2:0],
    output logic [7:0] result [4:0][4:0]
    );//#(parameter img_size=16,kernel_size=4)()

int i,j;

initial begin
    for(int i=0;i<5;i++) begin
        for(int j=0;j<5;j++) begin
            result[i][j]=8'b0;
        end
    end
end

always_ff @(posedge clk) begin
    for(i=0;i<5;i++) begin
        for(j=0;j<5;j++) begin
            for(int k=0;k<3;k++) begin
                for(int l=0;l<3;l++) begin
                    if ((i-k > -1)&&(j-l>-1)&&(i-k < 3)&&(j-l < 3))begin
                        result[i][j] <= result[i][j] + kernel[i-k][j-l]*img[k][l];
                    end
                end
            end
        end
    end
end

I actually wonder how you were able simulating your original code because my ModelSim just gives the error written by continuous and procedural assignments on the result (as you try initializing it in test and then modify in conv2d).

Related Solutions

Electronic – System verilog constraints

If your simulator supports it, you can use the $countones system function.

class random_error;
    rand bit[31:0] Var1;
    rand int unsigned N;
    constraint random_errorc { $countones(Var1) == N;};
endclass

module top;
    random_error r;
    initial begin
        r = new;
        for (int i = 0; i <= 32; i++) begin
            assert(r.randomize() with {N == i;});
            $display("r.N = %0d, r.Var1 = 32'b%032b", r.N, r.Var1);
        end
    end
endmodule

With Mentor Questa 10.0b, this produces the following output:

# r.N = 0, r.Var1 = 32'b00000000000000000000000000000000
# r.N = 1, r.Var1 = 32'b00000000000000000000000000000010
# r.N = 2, r.Var1 = 32'b00000000000000000000000001000100
# r.N = 3, r.Var1 = 32'b00000000000000000010100000000010
# r.N = 4, r.Var1 = 32'b00000000100100000000000000100010
# r.N = 5, r.Var1 = 32'b00010100000000010000010010000000
# r.N = 6, r.Var1 = 32'b00100010001000000000010000100100
# r.N = 7, r.Var1 = 32'b00001100000111000000100100000000
# r.N = 8, r.Var1 = 32'b01000100101000001010100000000100
# r.N = 9, r.Var1 = 32'b01000000000110100000100100011001
# r.N = 10, r.Var1 = 32'b10110000000000100000100110010101
# r.N = 11, r.Var1 = 32'b01100000010100110000000011010101
# r.N = 12, r.Var1 = 32'b10100110011100000001011001010000
# r.N = 13, r.Var1 = 32'b10001101101100010001010010011000
# r.N = 14, r.Var1 = 32'b01011010010100000100000110101111
# r.N = 15, r.Var1 = 32'b01000101010110110110010100011100
# r.N = 16, r.Var1 = 32'b11100101110110111000100000111000
# r.N = 17, r.Var1 = 32'b11010111101011000100100001110110
# r.N = 18, r.Var1 = 32'b11010101111011001010100101101001
# r.N = 19, r.Var1 = 32'b01100010001011111100101101101111
# r.N = 20, r.Var1 = 32'b10010110010110011111010110011111
# r.N = 21, r.Var1 = 32'b10101111001110111111111100001100
# r.N = 22, r.Var1 = 32'b01110111011101010111001100111111
# r.N = 23, r.Var1 = 32'b01011111010111111001111110011101
# r.N = 24, r.Var1 = 32'b00111110101101111101110111111101
# r.N = 25, r.Var1 = 32'b11111101110010111111011111111100
# r.N = 26, r.Var1 = 32'b11011110111011111111111111110010
# r.N = 27, r.Var1 = 32'b11001001111101111111111111111111
# r.N = 28, r.Var1 = 32'b11111000111111111111111011111111
# r.N = 29, r.Var1 = 32'b11111101111111111111111110101111
# r.N = 30, r.Var1 = 32'b11111111111111111111111110101111
# r.N = 31, r.Var1 = 32'b11111111111011111111111111111111
# r.N = 32, r.Var1 = 32'b11111111111111111111111111111111

Unfortunately, support for this depends on the simulator. I tried with Cadence Incisive 10.0 and it gives a compile error. If you cannot use $countones, there are other approaches to doing this.

See This link at verificationguild.com for a discussion of this.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

Related Solutions

Electronic – System verilog constraints

Electronic – Verilog asynchronous reads of regs – and design question

Related Topic