I'm trying to build a modulo-4 counter using dataflow modeling. I devised the logic circuit like the following;
simulate this circuit – Schematic created using CircuitLab
I wanted to implement this circuit with VHDL. I started from building an SR-latch. Then, a D-latch, then, a DFF. Finally I used the DFFs to build the circuit.
Following is my VHDL code for the counter,
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod4_counter is
Port (CLK : in std_logic; COUT : out std_logic);
end mod4_counter;
architecture Behavioral of mod4_counter is
component d_flipflop is
Port (DFF,CLK : in std_logic; QFF,QFFNOT : out std_logic );
end component;
signal dff1d, dff1q, dff1qnot, dff2d, dff2q, dff2qnot : std_logic;
begin
DFF1 : d_flipflop port map(DFF=>dff1d, CLK=>CLK, QFF=>dff1q,
QFFNOT=>dff1qnot);
DFF2 : d_flipflop port map(DFF=>dff2d, CLK=>CLK, QFF=>dff2q, QFFNOT=>dff2qnot);
dff1d <= dff1q xor dff2q;
dff2d <= dff2qnot;
COUT <= dff1q and dff2q;
end Behavioral;
And the testbench code,
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter_sim is
end counter_sim;
architecture Behavioral of counter_sim is
component mod4_counter is
Port (CLK : in std_logic; COUT : out std_logic );
end component;
signal CLK : std_logic;
signal COUT : std_logic;
begin
uut : mod4_counter port map(CLK=>CLK, COUT=>COUT);
clkpr : process
begin
CLK <= '1';
wait for 75ns;
CLK <= '0';
wait for 75ns;
end process;
end Behavioral;
All the underlying components (SR, D latch, DFF) were simulated successfully. But when I simulate this design, COUT is always 'X'. What is wrong here?
Best Answer
If you are only trying to implement your circuit then to me it seems that you are over thinking this: first let’s give NAME to the different signals:
simulate this circuit – Schematic created using CircuitLab
Now, let’s right the equations that rules the circuit:
Now, let's write the code:
You can remove the variables, I have added them for more clarity. You can also merge the 2 processes into a single one.
You should have a reset in your process.
I do not understand why you are talking about
SR-latch
,D-latch
orDFF
. In your schematic there is juste register (Flip-Flop).Hope it helps you