Electrical – What does low-impedance mean in the CMOS inverter circuit

Model level 3 definition: "Semi-empirical" - a more qualitative model that uses observed operation to define its equations. This dates from 1980 ... Any sort of decent result (i.e. within 10% of reality) would need to use level 5 models (AKA BSIM3). I'd recommend using BSIM 3V3 which is model level 49 in Star-HSPice parlance.

As long as you going to be using out of date models then you should heed your prof and only look at the trends. I suspect that there probably is a reason he said that.

You're dealing with curve fitted results.

Additionally, unless you have parasitic extraction enabled the rail capacitances as you noted are almost certainly not being extracted. The CJSW means Capacitance, Junction Side Wall and is a computed values based upon the width and S/D sizes (as one example). There are excellent SPICE guides that tell you what all the parameters are, I suggest you find and read them.

Logic gates get faster when the supply voltage increases. What you call the "time constant" of the charging path, isn't constant: it depends on supply voltage. If you think of it as an \$RC\$ circuit, the capacitance \$C\$ remains roughly constant, but \$R\$ decreases with supply voltage (remember that with increased \$V_{GS}\$ on a transistor, its resistance goes down), so \$RC\$ goes down.

A more accurate way to think of it is this: the voltage swing increases with supply voltage, so to maintain the same speed the charging current should also increase with supply voltage (remembering the capacitor equation, \$t=\frac{CV}{I}\$). However, for MOSFETs in saturation, the charging current increases roughly with the square of supply voltage (remembering the MOSFET equation, \$I_D=k(V_{GS}-V_{TH})^2\$). Thus, the time spent charging goes down.

This is true up to a point: once the transistors get small enough so that they no longer follow square-law behavior (because of velocity saturation), the logic gate speed no longer improves with increased supply voltage (because the charging current no longer scales with the square of \$V_{GS}\$, but instead scales linearly). Thus, for the latest process nodes, don't expect to improve speed by changing the supply voltage.