Electrical – Why are the outputs of these gates tied together in the Apollo Guidance Computer

digital-logichistorylogic-gatesopen-collectorschematics

In looking at the AGC schematics, I'm finding a lot of instances where the outputs of some of the NOR gates are tied together when feeding into another gate. The most dramatic example being here, where 4 NOR gates all have their outputs tied together.

More commonly though, the gates tied together look something like this:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

I can't imagine there'd be a reason for doing something like this in modern digital logic, since it seems like there'd be contention if one gate's output was low, and the other high.

So what's going on here, exactly? My first thought was that maybe it's some kind of "poor man's OR gate," allowing the next gate in the stage to see a high if at least one of the gates is high.

Is there some quirk with RTL logic that would allow it to work this way, or is the reason for this something else entirely?

Best Answer

RTL logic is open-collector, which allows the wire-OR connection (in this case, more precisely, wire-NOR.) The characteristic of wire-OR is that gates only drive low, so even if more than one is enabled, there is no clash. The gates share a common pullup resistor.

Wire-OR (that is, open-collector or open-drain) is still used. I2C for example is wire-OR. Wire-OR also is used for control signals where multiple devices share the same signal. Example: 'power good' from multiple voltage regulators, or interrupt pins from multiple devices.

The AGC's NOR IC supports a 'fan in' mode, where they connect the gate outputs without connecting the pull-up. In other words, when they connect multiple gates in wire-NOR, they designate only one to have the pull-up resistor, all the others have their pullup resistors left open. This is done to reduce power, and to ensure that the low-drive loading is kept within spec.

Here's the AGC’s NOR IC pinout: