System Verilog – Aggregate Value Error Solutions

system-verilogvga

I am working on a project and have encountered a problem with one of my modules.
I am trying to add offsets to 11 bits input from another model and output them to vga controller.
My inputs are declared like so –

input   logic signed  Player_TLX [10:0],     //Current Player Top Left X pos
input   logic signed  Player_TLY [10:0],    //Current Player Top Left Y pos

and the calculation I am trying to do are –

            if (Fire && !In_Air) begin //Projectile Launch
                    topLeftY_FixedPoint <= (Player_TLY + Player_Height)*FIXED_POINT_MULTIPLIER ;
                    topLeftX_FixedPoint <= Player_TLX + Player_Half_Width ;
                    In_Air <= TRUE ;
                    Enemy_Hit <= FALSE;
            end

Where player height, width and the multiplier are constants.
This lines give me the error –

Error (10686): SystemVerilog error at Projectile_moveCollision.sv(65): Player_TLY has an aggregate value
Error (10686): SystemVerilog error at Projectile_moveCollision.sv(66): Player_TLX has an aggregate value

I have tried using local parameters for the calculations but got similar error ,
is there a way to make such calculations?
am I using the wrong data type for this?
help would be appreciated.

Best Answer

You have the ranges in the declaration in the wrong place. You had an unpacked array of 11 single bits (an aggregate). You want a packed array of 11-bits (an integral)

input   logic signed  [10:0] Player_TLX,     //Current Player Top Left X pos
input   logic signed  [10:0] Player_TLY,    //Current Player Top Left Y pos

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Electronic – System Verilog seq.ended or seq.triggered

Based on the IEEE Std 1800-2005, ended is used inside an assertion, property, or another sequence (§ 17.7.10, ex @(posedge clk) reset ##1 inst ##1 my_seq.ended). triggered is is the equivalent to ended and is allowed outside of an assertion (§ 10.11, ex wait(my_seq.triggered)).

ended has been depreciated in IEEE Std 1800-2012 as mentioned in § C.2.3:

IEEE Std 1800-2005 17.7.3 required using the sequence method ended in sequence expressions and the sequence method triggered in other contexts. Since these two constructs have the same meaning but mutually exclusive usage contexts, in this version of the standard, the triggered method is allowed to be used in sequence expressions, and the usage of ended is deprecated and does not appear in this version of the standard.

Few if any simulators are 1800-2012 complaint, so follow with 1800-2005 for now.

Electronic – Instantiating multidimensional array in system verilog

First off, it is a common practice that parameters are upper case. When reading code this helps identify constants from variables. For arrays, refer to IEEE Std 1800-2012 § 7.4 Packed and unpacked arrays.

Packed means all the bits can be accessed at once or sliced
Unpacked means each index must be individually selected.

The following have the same dimensions:

logic [N-1:0] arr_up [M-1:0]; is M unpacked arrays, each with N packed bits
logic arr_uu [M-1:0] [N-1:0]; is M unpacked arrays, each with N unpacked single bits arrays
logic [M-1:0] [N-1:0] arr_pp; is M-by-N packed array, a slice of N-bits can be read out of the M index

Unpacked arrays can be initialized with a single digit: logic [N-1:0] arr_up [M]; is equivalent to logic [N-1:0] arr_up [0:M-1];. Do note that the [M] is [0:M-1] not [M-1:0].

The differences is in the access. All can access a single bit, but only packed bits can access a slice.

arr_up[M-2] = {{N{1'b0}}}; // legal
arr_uu[M-2] = {{N{1'b0}}}; // illegal, assigning packed to unpacked
arr_pp[M-2] = {{N{1'b0}}}; //legal`

arr_up[M-1:M-4] = {{3*N{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_uu[M-1:M-4] = {{3*N{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_pp[M-1:M-4] = {{3*N{1'b1}}}; // legal

arr_up[M-2][N-5] = 1'b0; // legal
arr_uu[M-2][N-5] = 1'b0; // legal
arr_pp[M-2][N-5] = 1'b0; // legal

arr_up[M-2][N-5:4] = {{N-9{1'b1}}}; // legal
arr_uu[M-2][N-5:4] = {{N-9{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_pp[M-2][N-5:4] = {{N-9{1'b1}}}; // legal

If the simulator is only accessing a single bit or index, unpacked arrays will give better performance. This is because packed arrays are accessed as a whole even if only one bit is being used. There is a balance between the simulators lookup overhead and number of lookup operations. Generally 2-D arrays are unpacked arrays of packed arrays. Adding dimensions is normal on the unpacked side. bytes, integers, words, and data buses are packed.

With typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} statetype;, be aware this is creating the definition of the state type. It is create a 2*N-bit array but only allows 4 values.

For an array of 4-state state machines, I would recommend:

typedef enum logic [1:0]{S0,S1,S2,S3} state_et;
state_et state[N], nextstate[N];

Best Answer

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