The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.
An SR Latch will look like this
In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)
An SR Flip-Flop (also called gated or clocked SR latch) looks like this.
In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.
I have been thinking about this definition a lot today.
As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, than right. I don't care what wikipedia says!
But in general:
- A flip flop will change it's output state at most once per clock cycle.
- A latch will change its state as many times as the data transitions during its transparency window.
Additionally,
- A flip flop is very safe. Almost fool-proof. For this reason synthesis tools usually use flip flops. But, they are slower than a latch (and use more power).
- Latches are harder to use properly. But, they are faster than flip flops (and smaller). So, custom circuit designers will often "spread the flip flop" across their digital block (a latch on either end with opposite phase) to squeeze some extra picoseconds out of a bad timing arc. This is shown at the bottom of the post.
A flip flop is most typically characterized by a master-slave topology. This is two coupled (there can be logic between), opposite phase latches back to back (sometimes in industry called L1/L2).
This means a flip flop inherently consists of two memory elements: one to hold during the low cycle and one to hold during the high cycle.
A latch is just a single memory element (SR latch, D latch, JK latch). Just because you introduce a clock to gate flow of data into the memory element does not make it a flip flop, in my opinion (although it can make it act like one: i.e. more rising edge triggered). It just makes it transparent for a specific amount of time.
Shown below is a true flip flop create from two SR latches (notice opposite phase clocks).
And another true flip-flop (this is the most common style in VLSI) from two D-latches (transmission gate style). Again notice the opposite phase clocks:
If you pulse the clock to a latch quickly enough, it starts to resemble a flip flop behavior (pulse latch). This is common in high speed datapath design because of the lesser delay from D->Out and Clk->Out, in addition to the better setup time granted (hold time also must increase, small price to pay) by transparency through the duration of the pulse. Does this make it a flip flop? Not really, but it sure looks acts like one!
However, this is much harder to guarantee to work. You must check across all process corners (fast nmos, slow pmos, high wire cap, low wire r; as an example of one) and all voltages (low voltage causes problems) that the pulse from your edge detector remains wide enough to actually open the latch and allow data in.
For your specific question, as to why it is considered a pulse latch instead of a flip flop, it is because you truly only have a single level sensitive bit storage element. Even though the pulse is narrow, it does not form a lock-and-dam system which creates a flip flop.
Here is an article describing a very similar pulse latch to your inquiry. A pertinent quote: "If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing."
EDIT
For some clarity I included a graphic of latch based design. There is a L1 latch and L2 latch with logic in between. This is a technique which can reduce delays, since a latch has lesser delay than a flip flop. The flip flop is "spread apart" and logic put in the middle. Now, you save a couple gate delays (compared to a flip flop on either end)!
Best Answer
To realize the point of a latch, consider that a flip flop is two back to back latches with opposite polarity clocks. This forms a lock-and-dam system which causes the output to change one cycle after the input (assuming setup and hold conditions are met).
So, the in->out path of a flip flop 'crosses' the cycle boundary. A circuit bound by flip flops will require two cycles for an input to show up at the output. If you only have a single cycle, you need to use a latch-bound circuit. This is essentially spreading out the two latches which comprise the flip flop and stuffing logic in between, instead of on either side (and causes the delay from input to output to be one cycle).
Below is an example of "spreading the flip flop" into its separate latches for a single cycle circuit:
Latches by themselves also allow much more flexibility in their usage. They allow "time-borrowing" which is a very powerful concept used all the time in VLSI design. In contrast, a standard flip flop only allows "time-stealing".
Below is a time-borrowing example with latches
And time-stealing with a flip flop:
On top of that, latches are almost exclusively used as the storage elements for clock or power gating circuits; they require less area/power than a flip-flop and accomplish the required job of storing a value (enable signal generally) across a half-cycle boundary.
As one further note, latches are often used in a way that mimics the flip-flop behavior. This is done by pulsing the clock very quickly; just long enough for whatever data is at the input to show up at the output, and not much longer. In this configuration, they are called pulse latches, as described by IEEE