I have a legacy expansion connector on an MCU board that I am looking to use in a new mode. I have full firmware control over all the pins going to the connector.
The interface has I2C SCL/SDA pins which are currently used. It also has currently unused SPI pins. However, when the board was first designed, only three SPI pins were defined: MOSI, MISO, and SCK, i.e. there is no chip select.
Since I can guarantee in the firmware that I2C and SPI transactions never overlap, I am considering re-purposing the SDA line as a chip select during SPI transactions.
To do this, at the start of the SPI transaction I would force the SDA line low through the GPIO control registers, run the transaction, and then reconnect the SDA line to the I2C controller so that it goes high again.
A side effect of using SDA to enable the SPI interface is that for every SPI transaction you generate a START condition (SDA H->L with SCL high) followed by a STOP condition (SDA L->H with SCL high), but with no data in between.
Does anyone know if START followed by STOP with nothing in between is a legal sequence of states on I2C?
Best Answer
From I2C specifications:
So, as per the specs, it is illegal, but in practice, it depends on the chips on the bus. Some I2C peripherals of MCUs do not like sequences that are not by the protocol, even though there is nothing wrong in theory about sending START and STOP.