I'm new to electrical (construction management student) and am trying to learn how to read start and end addresses. The practice problem I have been given is in the picture, and I was wondering how I would go about reading the start and end addresses of the entire section, as well as chips A and B in hexadecimal. The setup contains eight 2048×4 memory chips connected to a 16 bit address bus and 8 bit data bus
Best Answer
As an actual schematic, this drawing is a bit of a horror show.
The '1x4 DMUX' is a demux. The long-form description of that block is a '2-line to 4-line decoder/demultiplexer', available as a standard IC. I suppose you need to infer what pins are what since they're not labeled.
The SEL + upper address gate looks strange - it's drawn as a OR. It's a DeMorgan equivalent it seems. You'll need to work out that truth table.
One other thing. The 'circle' (bubble) on an input or output means inversion. So the select outputs to each RAM row are active-low. The drawing however isn't showing this inversion on the RAMs themselves, so this is an error / omission on the drawing.
Knowing all this, look at the address range of the RAM blocks, figure out what the upper address is doing along with ~SEL and that weird logic, and you should be able to derive the address range of the RAM set, and of each pair of RAMs (called a 'bank') in the set.