I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins).
How do I do this using Xilinx constraints (UCF file)? Can I group the block RAMs and define a single LOC constraint for the group or do I have to constrain every block RAM individually?
The main hurdle to me is that the number of block RAMs depends on a generic, which is why using one individual constraint for each block RAM seems not possible.
EDIT: The reason I am trying this approach is that my timing constraints can not be met. The timing errors are all related to the block RAMs of one module. Looking at the PAR result I can see that the critical block RAMs are scattered across the center of the FPGA, instead of being placed close to the relevant IO pins. Therefore I want to try to guide PAR into the direction where I think the block RAMs should be placed. The timing results should then tell me if my advice to PAR was helpful or not.
Best Answer
OK, so after some try and error, here is how I managed to do it:
First an AREA_GROUP which spans the part of the design which shall be constrained must be declared (in the projects UCF file).
This creates an AREA_GROUP containing everything in the design hierarchy "below" my_module. Now a range for the block RAMs within this AREA_GROUP can be defined.
The values for the range can be obtained from the vendors floorplanning tools (e.g. Xilinx ISE FPGA Editor). In the example above, all block RAMs (either inferred or instantiated) within my_module will be placed in the lower left corner of the FPGA. Since there are much more block RAMs available in that region (RANGE=RAMB8_X0Y0:RAMB8_X4Y12) than are required, this is no "hard" placement of the block RAMs, like achieved by the LOC constraint, but more flexible.
For details see http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/Floorplanning_Methodology_Guide.pdf