Electronic – Calculating MOSFET Heat Dissipation onto PCB

I'll just answer the NMOS part of your question. The answers for PMOS are similar, so the explanation should carry over.

a) Current flow through N-channel MOSFET transistor

1. Does not depend on V1's voltage
2. Depends on V2's voltage
3. Does not depend on the current charging the gate (from V2)

As long as you are operating the MOSFET in saturation, this is exactly what you expect. The relevant graph from the datasheet for your device is this:

When the gate-source voltage (in your schematic the voltage between N4 and N5) is high enough, only the gate-source voltage has a strong effect on the current through the MOSFET; the drain-source voltage (controlled by V1 in your circuit) has very little effect.

If you reduce V2 low enough, and by small enough steps, you should be able to trace out the roll off in the triode region, where both V1 and V2 will affect the current.

c) The current charging the gate is extremely low (about 0.0002fA).

This is exactly what you should see. The gate of the MOSFET is effectively a capacitor, and at DC will conduct almost no current.

b) Voltage across R3 is never higher than V2 - V1 (even if R3 resistance goes to infinity) > and it doesn't depend on the V1's voltage.

Again this is roughly what you should see, but V2 - V1 is not the relevant parameter, the threshold Vgs of the FET is. If R3's value is increased at constant current, it will reduce the difference between N4 and N5 voltages. That is, it will reduce the gate-source voltage of the MOSFET, until Vgs hits its "threshold" when the FET pretty much stops conducting altogether. So if R3 goes infinite, the MOSFET is shut off, and no current flows through R3. Despite R3 having a very high value, the voltage across R3 then becomes 0.

I have used an almost identical solution to this in various projects. First, be sure that whatever transistor you use to pull the gate of the p-channel mosfet in the power path can satisfy the Vgs criterion of that part. Second, make sure that the uC/Logic device you are interfacing with is protected from potentially unregulated voltage beyond its limits, this should be the function of the common cathode diode array you have shown in the schematic. If you trace out this circuits operation, you press the button, which pulls the cathode of the diode array to ground. This then causes the gate of the pmos device to go towards ground and turn on, this then causes all of your low side circuitry to power up. At this point your uC/Logic device is in a state to see that the button is indeed pressed, since its connection to the anode of one side of the array will cause some pin on that device to also be pulled to ground. The controlling device will then assert the gate/base of the nmos/npn transistor to switch and keep the pmos device on. So your understanding of the circuit is correct.

In terms of the operating conditions of the pchannel mosfet, all the Vgs term describes is the potential difference that must be seen at the gate for the device to "switch" (this isn't exactly correct, but for most purposes this description fits well enough) or saturate. So for instance, if a pchannel mosfet has a Vgs threshold of -3.0 V, then the voltage seen on the gate of the device must be lower than the voltage at the source minus 3.0 Volts. The pull up resistor on the gate is to bias the voltage to Vs so the transistor remains off until your apply some voltage from the rest of your circuit that satisfies the Vgs threshold requirement. Take a look at the NTS4173PT1G, Vgs threshold = -1.15V, so pulling it to ground surely will satisfy the criterion so long as the difference isn't above -12V. Surely I screwed up somewhere in my explanation, so take a looksie here AN-9010. The lowside mosfet I have used for this in the past is a good ol BSS138PW.

In terms of the regulator/converter you are choosing, that would depend on the input voltage, if you are feeding in a voltage somewhat close to the expected output of your regulator, than you should most likely stick with an LDO since it shouldn't be dissipating too much heat. However, if the difference is fairly large, or efficiency is of high concern to your application you should use a buck converter or the like. Look into the simple switcher line of components from TI, they are usually fairly simple to design with. Just be sure that the converter is sitting after the p-channel mosfet, that way it wont always be sitting on.