Electronic – Choosing Appropriate Bit Length

verilog

So, this has been bothering me for a couple semesters, and I guess I'm just too embarrassed to ask the professor for clarification, but I always feel a little in the dark about "choosing appropriate bit length" for output of binary arithmetic.

Say, for instance I am using verilog to code an adder that adds 3 10-bit 2's complement numbers, and will need to output a one-bit overflow detector. Should I choose the output to be 10-bit? Or should I increase it to 11 bit to avoid overflow for convenience?

I have no specific code as it's just a conceptual question.

Thanks!

Best Answer

If you adds two 10-bit 2's complement numbers, you need 11 bit to display all possible results. If you add three such words, you will need 12 bits. You may use only the 10 most significant bits of the result but you will loose precision.

If you know that all inputs are restricted to -170 < x < 170, 10 bits will be enough to hold all possible results.

If you use a 10 bit output plus a overflow signal, you do know the result is bigger than 511, but you don't know if it is larger or smaller than 1023.

I would like a solution that does not deliver false results without an error indication.

Related Solutions

Electronic – sequence detector in verilog

Your regs are defined wrong.

reg presentState ;
reg nextState ;

should be

reg [1:0] presentState ;
reg [1:0] nextState ;

By default, regs only have 1 bit so only states a and b can ever be reached.

Also, you should do your testbench a bit differently. Try

initial
begin
@(posedge clk);
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 

$finish;

end

instead.

With those couple of changes, I am getting a pulse on the 'tick' output when I run this in Icarus Verilog.

4 bit x 4 bit using look up table (rom)

assign P = ROM[(A * B)]; should be assign P = ROM[{A,B}]; The curly brackets ({}) is used to concatenate the bits. The square brackets ([]) are for indexing.

For ROM [(i * k)] = (i * k); you will want ROM [{i[3:0],k[3:0]}] = (i * k);

i and k are integers (equivalent to reg signed [31:0]), so {i,k} would be 64 bits wide with i starting at bit 32. The [3:0] is range slice if the integers that are meaningful for this indexing.

Note: you do not want to redefine i and k as reg [3:0] as this will give you an infinite loop 15 + 1 is 0 for a 4-bit reg and always less than 16.

Best Answer

Related Solutions

Electronic – sequence detector in verilog

4 bit x 4 bit using look up table (rom)

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