In terms of performance if you have say two inputs a and with the same bit width say 64. If you apply a bitwise operator and binary arithmetic operator (verilog/system verilog), which one takes longer to evaluate and why?
For example, in terms of a parity circuit when the parameters are change I observed a big difference in terms of simulation time while for an adder, the difference in simulation time isn't much. Code for adder and parity circuits are shown below.
module adder #(parameter width=64)(input logic [width-1 : 0] a, b, input cin, output logic cout, output logic [width-1:0] sum);
always @(a, b or carry_in) begin
{cout, sum} = a + b + cin;
end
endmodule
module eparity #(parameter width=128)(input logic [width-1 : 0] data, output logic p);
logic [width : 0] i_parity;
genvar i;
assign i_parity[0] = 0;
for(i = 0; i < width; i = i + 1) begin
assign i_parity[i+1] = data[i] ^ i_parity[i];
end
assign p = i_parity[width];
endmodule
Best Answer
The key difference in a bit wise operator is that the number of bits has no effect on performance—each bit operation is independent of the other bits. But once you get to arithmetic operators then there is a dependency from LSB to MSB that creates a long timing arc.
Updated Answer to an almost entirely different question
What you are seeing is a difference in the level of coding abstraction. Simulators can add two 64 bit numbers on the host machine in one cycle. But if you wrote out the addition in terms of a sequence of Boolean equations, that would certainly take more simulation time. If you wrote the parity equation as
That would certainly take less simulation time.