Electronic – Design of a counter that stays in each state for x clocks

counterdigital-logicfpgaverilog

Suppose we have an 8-bit counter out[7:0]

It needs to stay in each count for specified number of clocks x, where x can be any integer or fractional factor of 512.

My Approach:

Use 10 bit counter temp[9:0] that increments on every posedge clock

For x=512, increment temp in steps of 1, and increment out when temp[9]==1

For x=256, increment temp in steps of 2, and increment out when temp[9]==1
….and so on.

My Question

Does anyone have a better idea than this, more resource efficient?
How to handle the case when x can take arbitrary values not necessarily related by factors of a particular number? We only know the max that x can be.

To clarify: x is just a normal 9 bit register. The value in x and number of hold clocks are related by 512/x = HoldClocks.

512/1 = 512
512/2 = 256
512/3 = 170.667
512/4 = 128
……..
512/512 = 1.

How about the general case? What if max hold clocks isn't a power of 2? How would you handle the case where max hold clocks (x=1) is e.g 460 instead of 512?

Best Answer

Your question says "a particular state", but it sounds like you want out[7:0] to stay in each of its states for x clock cycles. If so, then you want to use temp[9:0] as a "prescaler" — for every x clocks, you want to send one pulse to the out counter. This works for any value of x.

For every clock cycle, check to see whether temp equals x-1. If so, set temp to zero and increment out; otherwise, just increment temp.

In Verilog:

always @(posedge clock) begin
  if (temp >= (x-1)) begin
    temp <= O;
    count <= count + 1;
  end else begin
    temp <= temp + 1;
  end
end

OK, now that the you have clarified the meaning of x, the following DDS code will implement what you want directly.

always @(posedge clock) begin
  temp <= (temp & 10'h1FF) + x;
  if (temp[9]) count <= count + 1;
end

If x=1, count will only increment once every 512 clocks. If x=512, count will increment on every clock. If x=40, count will increment every 12.8 clocks on average.

In the general case of having two numbers, where the counting rate is x/y (x must be no greater than y), think about what the code above is actually doing with respect to the value y=512:

What does the expression temp & 10'h1FF actually accomplish numerically?
Similarly, what does looking at bit 9 being set mean numerically?

Related Solutions

Electronic – On the use of “BLOCK INTERCLOCKDOMAIN PATHS”

What you are doing is correct. The key part is the synchronizer. If the only inter-clock domain nets are processed there, you can ignore the warning.

Your plan to remote constraints on other nets isn't the right plan. If you get warnings apart from your synchronizer, that means you have clock crossing elsewhere. You need to fix them.

Electronic – Generating pulse train of varying frequency on an FPGA

What you want to do is called a Numerically Controlled "Oscillator", or NCO. It works like this...

Create a counter that can increment by values other than 1. The inputs to this counter are the master clock, and a value to count by (din). For each clock edge, count <= count + din. The number of bits in din is the same as the number of bits in the counter. The actual count value can be used for many useful things, but what you want to do is super simple.

You want to detect every time the counter rolls over, and output a pulse to your motor when that happens. Do this by taking the most significant bit of the counter and running it through a single flip-flop to delay it by one clock. Now you have two signals that I'll call MSB, and MSB_Previous. You know if the counter has rolled over because MSB=0 and MSB_Prev=1. When that condition is true, send a pulse to the motor.

To set the pulse frequency, the formula is this: pulse_rate = main_clk_freq * inc_value/2^n_bits

Where inc_value is the value that the counter is being incremented by and n_bits is the number of bits in the counter.

An important thing to note is that adding bits to the counter does not change the range of the output frequency-- that is always 0 Hz to half of main_clk_freq. But it does change the accuracy that you can generate the desired frequency. Odds are high that you won't need 32-bits for this counter, and that maybe just 10 to 16 bits will be enough.

This method of generating pulses is nice because it is super easy, the logic is small and fast, and it can often generate frequencies more accurately and with better flexibility than the type of counter+comparator design that you have in your question.

The reason why the logic is smaller is not only because you can get by with a smaller counter, but you do not have to compare the entire output of the counter. You only need the top bit. Also, comparing two large numbers in an FPGA usually requires a lot of LUTs. Comparing two 32-bit numbers would require 21 4-Input LUTs and 3 logic levels, where as the NCO design requires 1 LUT, 2 Flip-Flops, and only 1 logic level. (I'm ignoring the counter, since it is basically the same for both designs.) The NCO approach is much smaller, much faster, much simpler, and yields better results.

Update: An alternative approach to making the rollover detector is to simply send out the MSB of the counter to the motor. If you do this, the signal going to the motor will always be a 50/50 duty cycle. Choosing the best approach depends on what kind of pulse your motor needs.

Update: Here is a VHDL code snippet for doing the NCO.

signal count :std_logic_vector (15 downto 0) := (others=>'0);
signal inc   :std_logic_vector (15 downto 0) := (others=>'0);
signal pulse :std_logic := '0';

. . .

process (clk)
begin
  if rising_edge(clk) then
    count <= count + inc;
  end if;
end process;

pulse <= count(count'high);

Best Answer

Related Solutions

Electronic – On the use of “BLOCK INTERCLOCKDOMAIN PATHS”

Electronic – Generating pulse train of varying frequency on an FPGA

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