Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
Electronic – Difference between RTL and Behavioral verilog
digital-logichdlverilogvhdl
Related Solutions
There is no difference, they mean exactly the same thing: infer my sensitivity list from the contents of the block.
Add (and use) a reset signal.
Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5). AFAIK, the @initial block is ignored.
However, things are chaotic when the FPGA starts up, because:
- The GSR is asynchronous.
- PLLs are not locked
- Not all PLLs lock at the same time
- There are race conditions everywhere
So the initial Flip-Flop values after the GSR are not enough.
Create a module that generates a reset signal for each clock domain. You can create it by by AND'ing relevant asynchronous reset signals, such as an external reset pin, PLL/DCM locked signals, and using it with a synchronizer, as follows:
(Source: How do I reset my FPGA?)
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Best Answer
Behavioral code is higher-level and usually can't be synthesized. Constructs like loops, delays, and "initial" statements are behavioral.
RTL code is lower-level and is intended to be synthesized. It defines a circuit as a combination of interconnected registers and the operations performed on signals between those registers.
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