If you use a flip flop, then changes in the combinational logic will only "appear" on the output of the flop on a clock edge. In general, with combinational logic, you will get all sorts of spurious transitions while the logic is "settling" on it's eventual value. If spurious transitions are a bad thing in your overall design (most likely they are), you will want to "filter them out" using a flip flop in this way. These transient changes in combinational outputs when inputs change are generally called "hazards."
In terms of the hardware you are generating in both cases, you will get the same combinational logic generated in your FPGA in both cases (out_ready || ~out_valid). The difference is, in the one case you are simply aliasing the output net of the combinational logic with the name in_ready, whereas in the other case you are connecting the output of the combinational logic to the input of a clocked flip flop.
In summary, there's nothing wrong with combinational logic, and you'd be hard pressed to design something useful in an FPGA that didn't include a bunch of it. Running the output through a flip flop isolates the next "stage" (i.e. the consumer) of your logic from seeing the spurious transitions of that logic that happen inherently when the inputs change (this design pattern, incidentally, is what pipelining - e.g. in modern CPUs - is all about). Remember to think of FPGAs and digital logic as hardware when writing Verilog (because that's what they are after all)!
Also, on a sidenote, determinism is not something that is measured on a sliding scale - something either is or is not deterministic, end of story.
Behavioral code is higher-level and usually can't be synthesized. Constructs like loops, delays, and "initial" statements are behavioral.
RTL code is lower-level and is intended to be synthesized. It defines a circuit as a combination of interconnected registers and the operations performed on signals between those registers.
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Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module to tailor it to your needs. If you decide to change the module later, you can just re-program it, and the gates will be re-arranged according to your changes.
On the other hand, hard cores are not user-editable. Sometimes, this is because the hard core is implemented with fixed hardware on the chip, rather than re-programmable logic.
A good example of these concepts is the Xilinx Zynq family of chips, which incorporate both hard and soft cores. Some of the space on the Zynq chip is provided as a permanent ARM-core processor, similar to what you'd find on any CPU chip. This region is the Programmable System (PS) and can be thought of as a 'hard' module, because that area cannot be re-used as some other module type. It's defined in hardware to be an ARM core. You can turn certain features on and off, but the logic module must reflect that the hardware is fixed.
However, the rest of the Zynq's chip area is re-programmable FPGA logic. You can define whatever modules you want to implement your design in the Programmable Logic (PL) region. Any modules implemented in the PL would be 'soft' modules, because they are reconfigurable.